TC11IB Datasheet, PDF (51/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
On-Chip Bus System
The TC11IB includes two bus systems:
– Local Memory Bus (LMB)
– On-Chip FPI Bus (Fast FPI and Slow FPI)
There are two bridges to interconnect these three buses. The LMB-to-FPI (LFI)
interfaces the Fast FPI bus to LMB Bus. The FPI-to-FPI (FFI) interfaces slow FPI bus to
Fast FPI bus.
Local Memory Bus (LMB)
The Local Memory Bus interconnects the memory units and functional units, such as
CPU and LMU. The main target of the LMB bus is to support devices with fast response
times, optimized for speed. This allows the DMU and PMU fast access to local memory
and reduces load on the FPI bus. The Tricore system itself is located on LMB bus. Via
External Bus Unit, it interconnects TC11IB and external components.
The Local Memory Bus is a synchronous, pipelined, split bus with variable block size
transfer support. It supports 8,16,32 & 64 bits single beat transactions and variable
length 64 bits block transfers.
Key Features
The LMB provides the following features:
• Synchronous, Pipelined, Multi-master, 64-bit high performance bus
• Support multiple bus masters
• Support Split transactions
• Support Variable block size transfer
• Burst Mode Read/Write to Memories
• Connect Caches and on-chip memory and Fast FPI Bus
Data Sheet
47
V2.3, 2003-11