TC11IB Datasheet, PDF (58/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
System Timer
The STM within the TC11IB is designed for global system timing applications requiring
both high precision and long range. The STM provides the following features:
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Driven by clock, f_STM (identical with the system clock f_SYS = 48MHz).
• Counting begins at power-on reset
• Continuous operation is not affected by any reset condition except power-on reset
The STM is an upward counter, running with the system clock frequency. It is enabled
per default after reset, and immediately starts counting up. Other than via reset, it is no
possible to affect the contents of the timer during normal operation of the application, it
can only be read, but not written to. Depending on the implementation of the clock control
of the STM, the timer can optionally be disabled or suspended for power-saving and
debugging purposes via a clock control register.
The maximum clock period is 2⁵⁶ × f_STM. At f_STM = 48 MHz, for example, the STM
counts 47.6 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life-time of a system without overflow.
f_STM
PORST
STM Module
55
47
39
31
23
15
7
56-Bit System Tim er
Enable /
Clock Disable
C o n tro l
Address
Decoder
00_H
CAP
00_H
T IM 6
T IM 5
TIM 4
T IM 3
T IM 2
TIM 1
T IM 0
Figure 14 Block Diagram of the STM Module
MCA04795
Data Sheet
54
V2.3, 2003-11