TC11IB Datasheet, PDF (55/108 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC11IB
The EBU is mainly used for the following two operations:
• Masters on LMB bus access external memories through EBU_LMB
• An external (off-chip) master access internal (on-chip) devices through FPI Bus.
The EBU controls all transactions required for these two operations and in particular
handles the arbitration of the external bus between multi-masters.
The types of external resources accessed by the EBU are:
• INTEL style peripherals (separate RD and WR signals)
• Motorola style peripherals (MR/ W signals)
• ROMs, EPROMs
• Static RAMs
• PC 100 SDRAMs (Burst Read/Write Capacity / Multi-Bank/Page support)
• Specific types of Burst Mode Flashes (Intel 28F800F3/28F160F3, AMD 29BL162)
• Special support for external emulator/debug hardware
Features
• Support Local Memory Bus (LMB 64-bit)
• Support External bus frequency up to 96 MHz and internal LMB frequency up to 166
MHz. External bus frequency: LMB frequency =1:1 or 1:2 or 1:4
• Highly programmable access parameters
• Support Intel-and Motorola-style peripherals/devices
• Support PC 100 SDRAM (burst access, multibanking, precharge, refresh)
• Support 16-and 32-bit SDRAM data bus and 64,128 and 256MBit devices
• Support Burst flash (Intel 28F800F3/160F3,AMD 29BL162)
• Support Multiplexed access (address &data on the same bus) when PC 100 SDRAM
is not implemented
• Support Address Alignment, external address space up to 64 MBytes.
• Support Data Buffering: Code Prefetch Buffer, Read/Write Buffer.
• External master arbitration compatible to C166 and other Tricore devices
• 8 programmable address regions (1 dedicated for emulator)
• Support Little-and Big-endian
• Signal for controlling data flow of slow-memory buffer
• Slave unit for external (off-chip) master to access devices on FPI bus
Data Sheet
51
V2.3, 2003-11