TLE9263-3QX Datasheet, PDF (45/198 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9263-3QX
5.4.3 Diagnoses Flags
5.4.3.1 PWRON/RESET-FLAG
The power-on reset can be detected and read by the POR bit in the SBC Status register.
The VS power on resets all register in the SBC to reset value. SWK is not configured.
5.4.3.2 BUSERR-Flag
Bus Dominant Time-out detection is implemented and signaled by CAN_Fail_x in register BUS_STAT_1.
5.4.3.3 TXD Dominant Time-out flag
TXD Dominant timeout is shown in the SPI bit CAN_FAIL_x in register BUS_STAT_1.
5.4.3.4 WUP Flag
The WUP bit in the SWK_STAT register shows that a Wake-Up Pattern (WUP) has caused a wake of the CAN
transceiver. It can also indicate an internal mode change from WUP detection 1 state to WUF detection after a
valid WUP.
In the following case the bit is set:
• SWK is activated: due to t_SILENCE, the CAN changes into the state WUP detection 1. If a WUP is detected in
this state, then the WUP bit is set
• SWK is deactivated: the WUP bit is set if a WUP wakes up the CAN. In addition, the CAN_WU bit is set.
• in case WUP is detected during WUP detection 2 state (after a SYSERR) the bits WUP and CAN_WU are set
The WUP bit is cleared automatically by the SBC at the next rearming of the CAN transceiver.
Note: It is possible that WUF and WUP bit are set at the same time if a WUF causes a wake out of SWK, by setting
the interrupt or by restart out of SBC Sleep Mode. The reason is because the CAN has been in WUP
detection 1 state during the time of SWK mode (because of t_SILENCE). See also Figure 11.
5.4.3.5 WUF Flag (WUF)
The WUF bit in the SWK_STAT register shows that a Wake-Up frame (WUF) has caused a wake of the CAN block.
In SBC Sleep Mode this wake causes a transition to SBC Restart Mode, in SBC Normal Mode and in SBC Stop
Mode it causes an interrupt. Also in case of this wake the bit CAN_WU in the register WK_STAT_1 is set.
The WUF bit is cleared automatically by the SBC at the next rearming of the CAN SWK function.
5.4.3.6 SYSERR Flag (SYSERR)
The bit SYSERR is set in case of an configuration error and in case of an error counter overflow. The bit is only
updated (set to ‘1’) if a CAN mode with SWK is enabled via CAN_x.
When programming selective wake via CAN_x, SYSERR = ‘0’ signals that the SWK function has been enabled.
The bit can be cleared via SPI. The bit is ‘0’ after Power on Reset of the SBC.
5.4.3.7 Configuration Error
A configuration error sets the SYSERR bit to ‘1’. When enabling SWK via the bits CAN_x a config check is done.
If the check is successful SWK is enabled, the bit SYSERR is set to ‘0’. In SBC Normal Mode it is also possible to
detect a Configuration Error while SWK is enabled. This will occur if the CFG_VAL bit is cleared, e.g. by changing
the SWK registers (from address 010 0001 to address 011 0011). In SBC Stop Mode and SBC Sleep Mode this
is not possible as the SWK registers can not be changed.
Data Sheet
45
Rev. 1.1, 2014-09-26