TLE9263-3QX Datasheet, PDF (133/198 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9263-3QX
Serial Peripheral Interface
16.2
Failure Signalization in the SPI Data Output
When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI
commands are either invalid SBC mode commands or commands which are prohibited by the state machine to
avoid undesired device or system states (see below). In this case the diagnosis bit ‘SPI_FAIL’ is set and the SPI
Write command is ignored (mostly no partial interpretation). This bit can be only reset by actively clearing it via a
SPI command.
Invalid SPI Commands leading to SPI_FAIL are listed below:
• Illegal state transitions: Going from SBC Stop to SBC Sleep Mode. In this case the SBC enters in addition the
SBC Restart Mode;
Trying to go to SBC Stop or SBC Sleep mode from SBC Init Mode. In this case SBC Normal Mode is entered;
• Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored or the new
watchdog settings are ignored respectively;
• In SBC Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration, PWM
settings and HS configuration settings during SBC Stop Mode, etc.;
the SPI command is ignored in this case;
only WD trigger, returning to Normal Mode, triggering a SBC Soft Reset, and Read & Clear status registers
commands are valid SPI commands in SBC Stop Mode;
• When entering SBC Stop Mode and WK_STAT_1 and WK_STAT_2 are not cleared; SPI_FAIL will not be set
but the INT pin will be triggered;
• Changing from SBC Stop to Normal Mode and changing the other bits of the M_S_CTRL register. The other
modifications will be ignored;
• SBC Sleep Mode: attempt to go to Sleep Mode when all bits in the BUS_CTRL_1, BUS_CTRL_2 and
WK_CTRL_2 registers are cleared. In this case the SPI_FAIL bit is set and the SBC enters Restart Mode.
Even though the Sleep Mode command is not entered in this case, the rest of the command (e.g modifying
VCC2 or VCC3) is executed and the values stay unchanged during SBC Restart Mode;
Note: At least one wake source must be activated in order to avoid a deadlock situation in SBC Sleep Mode,
i.e. the SBC would not be able to wake up anymore.
If the only wake source is a timer and the timer is OFF then the SBC will wake immediately from Sleep Mode
and enter Restart Mode;
No failure handling is done for the attempt to go to SBC STOP Mode when all bits in the registers
BUS_CTRL_1, BUS_CTRL_2 and WK_CTRL_2 are cleared because the microcontroller can leave this mode
via SPI;
• If VCC3 load sharing VCC3_LS is enabled and the microcontroller tries to clear the bit, then the rest of the
command executed but VCC3_LS will remain set;
• Attempt to enter SBC Sleep Mode if WK_MEAS is set to ‘1’ and only WK1_EN or WK2_EN are set as wake
sources. Also in this case the SPI_FAIL bit is set and the SBC enters Restart Mode;
• Setting a longer or equal on-time than the timer period of the respective timer;
• SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’;
Note: There is no SPI fail information for unused addresses.
Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 60):
The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set
for following conditions:
• in case the number of received SPI clocks is not 0 or 16,
• in case RO is LOW and SPI frames are being sent at the same time.
Data Sheet
133
Rev. 1.1, 2014-09-26