TLE9263-3QX Datasheet, PDF (143/198 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9263-3QX
Serial Peripheral Interface
2. After triggering a SBC Soft Reset the bits VCC3_V_CFG and VCC3_LS are not reset if they were set before,
i.e. it stays unchanged, which is stated by the ‘y’ in the POR / Soft Reset Value. POR value: 0000 0000 and
Soft Reset value: xx00 x00x
3. VCC3_LS_STP_ON: Is a combination of load sharing and VCC1 active peak in Stop mode
WD_CTRL
Watchdog Control (Address 000 0011_B)
POR / Soft Reset Value: 0001 0100_B; Restart Value: x0xx 0100_B
7
6
5
4
3
2
1
0
CHECKSUM
rw
WD_STM_
EN_0
rwh
WD_WIN
rw
WD_EN_
WK_BUS
rw
Reserved WD_TIMER_2 WD_TIMER_1 WD_TIMER_0
r
r
rwh
rwh
rwh
Field
Bits
CHECKSUM 7
WD_STM_ 6
EN_0
WD_WIN 5
WD_EN_ 4
WK_BUS
Reserved 3
WD_TIMER 2:0
Type
rw
rwh
rw
rwh
r
rwh
Description
Watchdog Setting Check Sum Bit
The sum of bits 7:0 needs to have even parity (see Chapter 15.2.3)
0_B , Counts as 0 for checksum calculation
1_B , Counts as 1 for checksum calculation
Watchdog Deactivation during Stop Mode, bit 0 (Chapter 15.2.4)
0_B , Watchdog is active in Stop Mode
1_B , Watchdog is deactivated in Stop Mode
Watchdog Type Selection
0_B , Watchdog works as a Time-Out watchdog
1_B , Watchdog works as a Window watchdog
Watchdog Enable after Bus (CAN/LIN) Wake in SBC Stop Mode
0_B , Watchdog will not start after a CAN/LINx wake
1_B , Watchdog starts with a long open window after CAN/LINx
Wake
Reserved, always reads as 0
Watchdog Timer Period
000_B , 10ms
001_B , 20ms
010_B , 50ms
011_B , 100ms
100_B , 200ms
101_B , 500ms
110_B , 1000ms
111_B , reserved
Notes
1. See also Chapter 15.2.4 for more information on disabling the watchdog in SBC Stop Mode.
2. See Chapter 15.2.5 for more information on the effect of the bit WD_EN_WK_BUS.
3. See Chapter 15.2.3 for calculation of checksum.
Data Sheet
143
Rev. 1.1, 2014-09-26