TLE9263-3QX Datasheet, PDF (134/198 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9263-3QX
Serial Peripheral Interface
Note: In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is not
valid if the CLK is high on a falling edge of CSN
The number of received SPI clocks is not 0 or 16:
The number of received input clocks is supervised to be 0- or 16 clock cycles and the input word is discarded in
case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high
during CSN edges. Both errors - 0 bit and 16 bit CLK mismatch or CLK high during CSN edges - are flagged in
the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the clock
is received. The complete SPI command is ignored in this case.
RO is LOW and SPI frames are being sent at the same time:
The ERR flag will be set when the RO pin is triggered (during SBC Restart) and SPI frames are being sent to the
SBC at the same time. The behavior of the ERR flag will be signalized at the next SPI command for below
conditions:
• if the command begins when RO is HIGH and it ends when RO is LOW,
• if a SPI command will be sent while RO is LOW,
• If a SPI command begins when RO is LOW and it ends when RO is HIGH.
and the SDO output will behave as follows:
• always when RO is LOW then SDO will be HIGH,
• when a SPI command begins with RO is LOW and ends when RO is HIGH, then the SDO should be ignored
because wrong data will be sent.
Note: It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled low
and SDO is observed - no SPI Clocks are sent in this case
Note: The ERR flag could also be set after the SBC has entered SBC Fail-Safe Mode because the SPI
communication is stopped immediately.
Data Sheet
134
Rev. 1.1, 2014-09-26