TLE9263-3QX Datasheet, PDF (110/198 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

13
Interrupt Function
13.1
Block and Functional Description
TLE9263-3QX
Interrupt Function
V_{c c 1}
INT
Time
Interrupt logic
out
Figure 47 Interrupt Block Diagram
The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is designed
as a push/pull output stage as shown in Figure 47. An interrupt is triggered and the INT pin is pulled low (active
low) for t_INT in SBC Normal and Stop Mode and it is released again once t_INT is expired. The minimum HIGH-time
of INT between two consecutive interrupts is t_INTD. An interrupt does not cause a SBC mode change.
Two different interrupt classes could be selected via the SPI bit INT_ GLOBAL:
• Class 1 (wake interrupt - INT_ GLOBAL=0): all wake-up events stored in the wake status SPI register
(WK_STAT_1 and WK_STAT_2) cause an interrupt (default setting). An interrupt is only triggered if the
respective function is also enabled as a wake source (including GPIOx if configured as a wake input). The CAN
time out signalization CANTO is also considered as a wake source. Therefore, the interrupt mask bit CANTO_
MASK has higher priority than the bit INT_ GLOBAL, i.e. Integral is not taken into account for CANTO.
• Class 2 (global interrupt - INT_ GLOBAL=1): in addition to the wake-up events, all signalled failures stored in
the other status registers cause an interrupt (the register WK_LVL_STAT is not generating interrupts)
Note: The errors which will cause SBC Restart or SBC Fail-Safe Mode (Vcc1_UV, WD_FAIL, VCC1_SC, TSD2,
FAILURE) are the exceptions of an INT generation on status bits. Also POR and DEV_STAT_x and will not
generate interrupts.
In addition to this behavior, an INT will be triggered when the SBC is sent to SBC Stop Mode and not all bits were
cleared in the WK_STAT_1 and WK_STAT_2register.
The SPI status registers are updated at every falling edge of the INT pulse. All interrupt events are stored in the
respective register (except the register WK_LVL_STAT) until the register is read and cleared via SPI command.
A second SPI read after reading out the respective status register is optional but recommended to verify that the
interrupt event is not present anymore. The interrupt behavior is shown in Figure 48 for class 1 interrupts. The
behavior for class 2 is identical.
The INT pin is also used during SBC Init Mode to select the hardware configuration of the device. See
Chapter 5.1.1 for further information.
Data Sheet
110
Rev. 1.1, 2014-09-26