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82P33741 Datasheet, PDF (56/61 Pages) Integrated Circuit Systems – Differential reference inputs
82P33741 Datasheet
8.5 INPUT / OUTPUT CLOCK TIMING
The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs.
Input Clock
Output Clock
t1
Figure 25. Input / output clock timing
Table 40: Input-to-Output Delay via APLL1/2
Output
Min (ns)
Max (ns)
Range (nspp)
Any LVCMOS Input to any of OUT01, OUT02 or
OUT07
13
19
6
(±3 around mean)
Any LVPECL/LVDS Input to any of OUT03, OUT04,
OUT5 or OUT06
11.5
16.5
5
(±2.5 around mean)
Any Input to any APLL1/2 Output
10
19
9
(±4.5 around mean)
Any Input to [M]FRSYNC Output
0
8
8
(typical value is 2.5ns)
NOTE 1. The measurements in the above table takes into account any delays in the clock path from any input to any output; through either DPLL1 or DPLL2 and the
either APLL1 or APLL2.
NOTE 2. The measurements in the above table are over operational temperature, varying power supply and repeated power on/off cycle.
NOTE 3. Measurements are taken using an ideal REF input and an ideal System clock to account for only internal delays in the device.
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Revision 6, July 21, 2016