82P33741 Datasheet, PDF (21/61 Pages) Integrated Circuit Systems – Differential reference inputs

Rejecting threshold
Accepting threshold
82P33741 Datasheet
accepted
rejected (alarmed)
accepted
Figure 8. Hysteresis Frequency Monitoring
3.1.3.3 Input Clock Selection
For DPLL1, DPLL2 and DPLL3, the DPLL1/2/3_INPUT_SEL[3:0] bits
(register DPLL1/2/3_input_sel_cnfg) determine the input clock selection,
as shown in Table 8:
Table 8: Input Clock Selection for DPLL1, DPLL2 and DPLL3
DPLL1/2/3 _INPUT_SEL[3:0]
0000
0001 ~ 1110
1111
Input Clock Selection
Automatic selection
Forced selection (IN1 ~ IN14)
Reserved
3.1.3.3.1 Forced Selection
In Forced selection, the selected input clock is set by the DPLL1_IN-
PUT_SEL[3:0], DPLL2_INPUT_SEL[3:0], and DPLL3_INPUT_SEL[4:0]
bits. The results of input clocks quality monitoring do not affect the input
clock selection if Forced selection is used.
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Revision 6, July 21, 2016