82P33741 Datasheet, PDF (3/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
HIGHLIGHTS ........................................................................................................................................................................... 5
FEATURES .............................................................................................................................................................................. 5
APPLICATIONS....................................................................................................................................................................... 5
DESCRIPTION......................................................................................................................................................................... 6
FUNCTIONAL BLOCK DIAGRAM .......................................................................................................................................... 7
1 PIN ASSIGNMENT ............................................................................................................................................................. 8
2 PIN DESCRIPTION ............................................................................................................................................................ 9
2.1 RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS ........................................................................................................... 12
2.1.1 Inputs .............................................................................................................................................................................................. 12
2.1.2 Outputs ........................................................................................................................................................................................... 12
2.2 RESET OPERATION ..................................................................................................................................................................................... 13
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 14
3.1 HARDWARE FUNCTIONAL DESCRIPTION ................................................................................................................................................ 14
3.1.1 System clock .................................................................................................................................................................................. 14
3.1.2 Modes of operation ........................................................................................................................................................................ 14
3.1.2.1 DPLL1 and DPLL2 Operating Mode ................................................................................................................................. 14
3.1.2.2 DPLL3 Operating Mode ................................................................................................................................................... 17
3.1.3 Input Clocks and frame sync ........................................................................................................................................................ 18
3.1.3.1 Input Clock Pre-divider ..................................................................................................................................................... 18
3.1.3.2 Input Clock Quality Monitoring ......................................................................................................................................... 19
3.1.3.3 Input Clock Selection ........................................................................................................................................................ 21
3.1.4 DPLL Locking Process .................................................................................................................................................................. 23
3.1.4.1 Fast Loss .......................................................................................................................................................................... 23
3.1.4.2 Coarse Phase Loss .......................................................................................................................................................... 23
3.1.4.3 Fine Phase Loss ............................................................................................................................................................... 23
3.1.4.4 Hard Limit Exceeding ....................................................................................................................................................... 23
3.1.4.5 Locking Status .................................................................................................................................................................. 24
3.1.4.6 Phase Lock Alarm ............................................................................................................................................................ 24
3.1.5 APLL1 and APLL2 .......................................................................................................................................................................... 24
3.1.6 APLL3 .............................................................................................................................................................................................. 25
3.1.6.1 External Crystals .............................................................................................................................................................. 25
3.1.7 Output Clocks & Frame Sync Signals .......................................................................................................................................... 26
3.1.7.1 Output Clocks ................................................................................................................................................................... 26
3.1.7.2 Frame Sync Signals ......................................................................................................................................................... 27
3.1.8 Input and output Phase control .................................................................................................................................................... 28
3.1.8.1 DPLL1 and DPLL2 Phase offset control ........................................................................................................................... 28
3.1.8.2 Input Phase control .......................................................................................................................................................... 28
3.1.8.3 Output Phase control ........................................................................................................................................................ 28
4 POWER SUPPLY FILTERING TECHNIQUES ................................................................................................................. 29
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 31
5.1 I2C SLAVE MODE ......................................................................................................................................................................................... 31
5.1.1 I2C Device Address ........................................................................................................................................................................ 31
5.1.2 I2C Bus Timing ............................................................................................................................................................................... 31
5.1.3 Supported Transactions ................................................................................................................................................................ 33
5.2 I2C MASTER MODE ..................................................................................................................................................................................... 33
5.2.1 I2C Boot-up Initialization Mode ..................................................................................................................................................... 34
5.2.2 EEPROM memory map notes ........................................................................................................................................................ 34
6 JTAG ................................................................................................................................................................................ 35
7 THERMAL MANAGEMENT ............................................................................................................................................. 36
7.1 JUNCTION TEMPERATURE ........................................................................................................................................................................ 36
7.2 THERMAL RELEASE PATH ......................................................................................................................................................................... 36
©2016 Integrated Device Technology, Inc.
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Revision 6, July 21, 2016