82P33741 Datasheet, PDF (53/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
Table 36: SONET/SDH Output Clock Jitter Generation
(jitter measured on one differential output of APLL1/2 with one differential output enabled)
Output Frequency
RMS Jitter Typ (ps)
RMS Jitter Max (ps)
Test Filter
0.55
0.82
12 kHz to 20 MHz
0.87
0.81
155.52 MHz
0.65
0.29
0.21
0.20
NOTE 1: DPLL locked to input clock
1.52
500 Hz to 1.3 MHz
1.43
1 kHz to 5 MHz
1.03
5 kHz to 20 MHz
0.41
65 kHz to 1.3 MHz
0.30
250 kHz to 5 MHz
0.26
1 MHz to 20 MHz
Notes
GR-253-CORE and ITU-T
G.813 Option 2
limit 0.1 UI p-p /
0.01 UI RMS
(STM-16: 1UI = 0.40 ns)
ITU-T G.813 Option 1
limit 0.5 UI p-p
(STM-1: 1 UI = 6.43 ns)
ITU-T G.813 Option 1
limit 0.5 UI p-p
(STM-4: 1 UI = 1.61 ns)
ITU-T G.813 Option 1
limit 0.5 UI p-p
(STM-16: 1UI = 0.40 ns)
ITU-T G.813 Option 1
limit 0.1 UI p-p
(STM-1: 1 UI = 6.43 ns)
ITU-T G.813 Option 1
limit 0.1 UI p-p
(STM-4: 1 UI = 1.61 ns)
ITU-T G.813 Option 1
limit 0.1 UI p-p
(STM-16: 1UI = 0.40 ns)
©2016 Integrated Device Technology, Inc.
53
Revision 6, July 21, 2016