82P33741 Datasheet, PDF (17/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
3.1.2.1.8 Phase Slope Limit
Both DPLL1 and DPLL2 provide a phase slope limiting feature to limit
the rate of output phase movement. The limit level is selectable via
DPLL1/2_ph_limit[1:0] bits in DPLL1/2_bw_overshoot_cnfg register. The
options are shown in Table 5.
Table 5: DPLL1/2 Phase Slope Limit
DPLL1/2_ph_limit[1:0]
Phase Slope Limit
00
61µs/s (GR-1244 ST3)
885ns/s (GR-1244-CORE ST2 and 3E,
01
GR-253-CORE ST3 and
G.8262 EEC option 2)
10
7.5 µs/s (G.813 opt1, G.8262 EEC-
option 1)
11
unlimited / 1.4 ms/s (default)
*Note: The default phase slope limiting is set to 0 ns/s, therefore, the phase
slope limiting must be set to the proper value to meet different standards
according to this table. For PSL = 885 ns/s, it is recommended that a TCXO be
used.
3.1.2.1.9 Phase and Frequency Detector PFD Output Limit
The PFD output is limited to be within ±1 UI or within the coarse
phase limit (refer to Chapter 3.1.4.2), as determined by the MUL-
TI_PH_APP bit.
3.1.2.1.10 Frequency Offset Limit
The DPLL1/2 output is limited to be within the programmed DPLL
hard limit (refer to Chapter 3.1.4.4).
3.1.2.2 DPLL3 Operating Mode
The DPLL3 operating mode is controlled by the DPLL3_OPERAT-
ING_MODE[2:0] bits, as shown in Table 6. DPLL3 is disabled by default,
write “0” to bit DPLL3_dpll_pdn in pdn_conf register to enable it.
Table 6: DPLL3 Operating Mode Control
DPLL3_OPERATING_MODE[2:0]
000
001
010
100
DPLL3 Operating Mode
Automatic
Forced - Free-Run
Forced - Holdover
Forced - Locked
When the operating mode is switched automatically, the operation of
the internal state machine is shown in Figure 5:
1
Free-Run mode
2
Locked mode
3
4
Holdover
mode
5
Figure 5. DPLL3 Automatic Operating Mode
Notes to Figure 5:
1. Reset.
2. An input clock is selected.
3. (The DPLL3 selected input clock is disqualified) OR (A qualified
input clock with a higher priority is switched to) OR (The DPLL3
selected input clock is switched to another one by Forced selec-
tion).
4. An input clock is selected.
5. No input clock is selected.
3.1.2.2.1 Free-Run Mode
In Free-Run mode, the DPLL3 output refers to the system clock and
is not affected by any input clock. The accuracy of the DPLL3 output is
equal to that of the system clock.
3.1.2.2.2 Locked Mode
In Locked mode, the DPLL3 is locked to the input clock. The phase
and frequency offset of the DPLL3 output track those of the DPLL3
selected input clock.
DPLL3 is a wide BW DPLL, with loop bandwidth higher than 25Hz.
©2016 Integrated Device Technology, Inc.
17
Revision 6, July 21, 2016