82P33741 Datasheet, PDF (26/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
3.1.7 OUTPUT CLOCKS & FRAME SYNC SIGNALS
The device supports 11 output clocks and 2 frame sync output sig-
nals.
3.1.7.1 Output Clocks
OUT1 can be derived either from DPLL1, DPLL2, or APLL1 selected
by out1_mux_cnfg[3:0]
OUT2 ~ OUT4 can be derived from APLL1.
OUT5 ~ OUT7 can be derived from APLL2.
OUT1 to OUT7 have an output divider associated with each output.
The divider is composed by 2 cascaded dividers, the first divider can be
programmed by writing into OUTn_DIV1_CNFG[4:0], the second divider
can be programmed by writing into OUTn_DIV2_CNFG[26:0].
Figure 10 shows the diagram for OUT1 output dividers and relevant
register bits.
APLL_PATH
OUT1_MUX_CNFG[3:0]
DPLL1
DPLL2
APLL1
Output Divider
Output Div1
(OUT1_DIV1_CNFG[4:0]
Phase 1
Output Div2
(OUT1_DIV2_CNFG[26:0]
Phase 2
OUT1
Figure 10. OUT1 output dividers
Figure 11 shows the diagram for OUT2 to OUT7 output dividers and
relevant register bits.
APLL_PATH
DPLL1
DPLL2
APLL1
APLL2
Output Dividers
Output Div1
(OUTn_DIV1_CNFG[4:0]
2<n<4 (from APLL1)
5<n<7 (from APLL2)
Phase 1
Output Div2
(OUTn_DIV2_CNFG[26:0]
2<n<4 (from APLL1)
5<n<7 (from APLL2)
Phase 2
2<n<4 (from APLL1)
OUTn _{5<n<7 (from APLL2)}
Figure 11. OUT2 to OUT7 output dividers
OUT8 and OUT9 are derived from DPLL3, there is an output divider
associated with it. A GUI (Time Commander) can be used to set the fol-
lowing bis in the respective register that are associated with the DPLL3
dividers.
• To set the feedback divider, program dpll3_fb_div_cnfg[13:0] bits
of DPLL3 feedback divider register
• To set the fractional divider, program dpll3_divn_frac_cnfg[23:0]
of DPLL3 fractional divider register
• To set the denominator of the fractional divider, program
dpll3_divn_den_cnfg[15:0] bits of DPLL3 fractional divider
denominator register
• To set the numerator of the fractional divider, program
dpll3_divn_num_cnfg[15:0] bits of DPLL3 fractional divider
numerator register
• To set the integer divider, program dpll3_int_cnfg[7:0]bits of
DPLL3 integer divider register
OUT10 and OUT11 are derived from APLL3, refer to Table 14 for the
output frequency.
©2016 Integrated Device Technology, Inc.
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Revision 6, July 21, 2016