82P33741 Datasheet, PDF (19/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
When the DivN divider is used for INn (1  n  12), the division factor
setting should observe the following order:
1. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
2. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
The division factor is calculated as follows:
Division Factor = (the frequency of the clock input to the DivN
divider ÷ the frequency of the DPLL required clock set by the IN_-
FREQ[3:0] bits) - 1
The Pre-divider configuration and the division factor setting depend
on the input clock on one of the IN3 ~ IN14 pins and the DPLL required
clock.
For the fractional input divider, the FEC divider, each input clock has
a 16-bit (fec_divp_cnfg[15:0]) that represents the value of the numerator
and a 16-bit (fec_divq_cnfg[15:0]) that represents the value of the
denominator of FEC divider. The FEC division factor is calculated as fol-
lows:
FEC Division Factor = (fec_divp_cnfg[15:0]) ÷
(fec_divq_cnfg[15:0])
Pre-Divider
INn_DIV[1:0] bits
1<n<6
Input Clock INn
1 < n < 12
HF Divider
(for IN1 ~ IN6)
1
FEC Divider (P/Q)
0
DIRECT_DIV bit
LOCK_8K bit
00
DPLL
Clock
DivN Divider
1< n < 19440
01
Figure 6. Pre-divider for an input clock
3.1.3.2 Input Clock Quality Monitoring
The qualities of all the input clocks are always monitored in the fol-
lowing aspects:
• Activity
• Frequency
LOS monitoring is only conducted on IN1 and IN2. Activity and fre-
quency monitoring are conducted on all the input clocks.
The qualified clocks are available for selection for all 3 DPLLs.
3.1.3.2.1 Activity Monitoring
Activity is monitored by using an internal leaky bucket accumulator,
as shown in Figure 7.
Each input clock is assigned an internal leaky bucket accumulator.
The input clock is monitored for each period of 128 ms, the internal leaky
bucket accumulator is increased by 1 when an event is detected; and it
is decreased by 1 when no event is detected within the period set by the
decay rate. The event is that an input clock drifts outside (>) ±500 ppm
with respect to the system clock within a 128 ms period.
There are four configurations (0 - 3) for a leaky bucket accumulator.
The leaky bucket configuration for an input clock is selected by the cor-
responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
The bucket size is the capability of the accumulator. If the number of
the accumulated events reach the bucket size, the accumulator will stop
increasing even if further events are detected. The upper threshold is a
point above which a no-activity alarm is raised. The lower threshold is a
point below which the no-activity alarm is cleared. The decay rate is a
certain period during which the accumulator decreases by 1 if no event
is detected.
The leaky bucket configuration is programmed by one of four groups
of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_
THRESHOLD_n_DATA[7:0] bits, the LOWER_THRESHOLD_n_
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 0 ~ 3.
The no-activity alarm status of the input clock is indicated by the
INn_NO_ACTIVITY_ALARM bit (12  n  1).
The input clock with a no-activity alarm is disqualified for clock selec-
tion for the DPLLs.
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Revision 6, July 21, 2016