82P33741 Datasheet, PDF (47/61 Pages) Integrated Circuit Systems – Differential reference inputs

Table 32: Gigabit Ethernet Output Clock Jitter Generation
(jitter measured on one differential output of APLL1/2 with one differential output enabled)
Output Frequency
RMS Jitter Typ (ps)
RMS Jitter Max (ps)
0.56
0.85
0.52
0.99
156.25MHz
0.23
0.30
Test Filter
12 kHz - 20 MHz
20 kHz - 40 MHz
1 MHz - 30 MHz
0.16
0.22
1.875 MHz - 20 MHz
NOTE 1: DPLL locked to input clock
NOTE 2: For BER = 10–12, RMS jitter = p-p jitter/13.8 per IEEE 802.3-2008 and IEEE 802.3ae-2002 section 48B.3.1.3.1
Table 33: Gigabit Ethernet Output Clock Jitter Generation
(Jitter measured on one CMOS output of APLL1/2 with one CMOS output enabled)
Output Frequency
RMS Jitter Typ (ps)
RMS Jitter Max (ps)
0.71
1.26
25 MHz
0.55
0.83
0.23
0.30
Test Filter
2.5 kHz - 5 MHz
12 kHz - 5 MHz
637 kHz - 5 MHz
0.78
125MHz
0.62
0.21
2.32
2.5 kHz to 10 MHz
0.94
12 kHz - 20 MHz
0.31
637 kHz - 10 MHz
NOTE 1: DPLL locked to input clock
NOTE 2: For BER = 10–12, RMS jitter = p-p jitter/13.8 per IEEE 802.3-2008 and IEEE 802.3ae-2002 section 48B.3.1.3.1
82P33741 Datasheet
Notes
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 100.47 ps)
IEEE 802.3-2008
limit 0.28 UI p-p /
0.0203 UI RMS
(1 UI = 100.47 ps)
Notes
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 0.8 ns)
IEEE 802.3-2008
limit 0.24 UI p-p /
0.0174 UI RMS
(1 UI = 0.8 ns)
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 0.8 ns)
IEEE 802.3-2008
limit 0.24 UI p-p /
0.0174 UI RMS
(1 UI = 0.8 ns)
©2016 Integrated Device Technology, Inc.
47
Revision 6, July 21, 2016