82P33741 Datasheet, PDF (16/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
3.1.2.1.1 Free-Run Mode
In Free-Run mode, the DPLL1/2 output refers to the system clock
and is not affected by any input clock. The accuracy of the DPLL1/2 out-
put is equal to that of the system clock.
3.1.2.1.2 Pre-Locked Mode
In Pre-Locked mode, the DPLL1/2 output attempts to track the
selected input clock.
The Pre-Locked mode is a secondary, temporary mode.
3.1.2.1.3 Locked Mode
In Locked mode, the DPLL1/2 is locked to the input clock. The phase
and frequency offset of the DPLL1/2 output track those of the DPLL1/2
selected input clock.
For a closed loop, different bandwidths and damping factors can be
used. They are set by the DPLL1/2_LOCKED_BW[4:0] bits and the
DPLL1/2_LOCKED_DAMPING[2:0] bits respectively. DPLL1/
2_LOCKED_BW[4] must be set to 1.
The locked bandwidth is selectable can be set as shown in Table 4.
Table 4: DPLL1/2 Locked Bandwidth
DPLL1/2_LOCKED_BW[3:0]
0000
0001
0010
0011
0100
0101
0110-1111
BW
18 Hz
35 Hz
71 Hz
142 Hz
283 Hz
567 Hz
Reserved
3.1.2.1.4 Pre-Locked2 Mode
In Pre-Locked2 mode, the DPLL1/2 output attempts to track the
selected input clock.
The Pre-Locked2 mode is a secondary, temporary mode.
3.1.2.1.5 Lost-Phase Mode
In Lost-Phase mode, the DPLL1/2 output attempts to track the
selected input clock.
The Lost-Phase mode is a secondary, temporary mode.
3.1.2.1.6 Holdover Mode
In Holdover mode, the DPLL1/2 resorts to the stored frequency data
acquired in Locked mode to control its output. The DPLL1/2 output is not
phase locked to any input clock.
The holdover mode is set to current averaged value with holdover fil-
ter BW of ~1.5mHz. In this mode the initial frequency offset is better than
1.1e-5ppm assuming that there is no in-band jitter/wander at the input
just before entering holdover state.
The offset value can be read from the holdover_freq_cnfg[39:0] bits
by setting the read_avg bit to “1”.
The holdover frequency resolution is calculated as follows:
Holdover Frequency resolution: HO_freq_res = (77760/1638400) *
2^-48
The Holdover value read from register bits holdover_freq_cnfg[[39:0]
must be converted to decimal:
HO_value_dec = holdover_freq_cnfg[39:0] value in decimal
The frequency offset in ppm is calculated as follows:
Holdover Frequency Offset (ppm) = (HO_freq_res * HO_value_dec)/
(1-((HO_freq_res * HO_value_dec)/1e6))
3.1.2.1.7 Hitless Reference Switching
Bit hitless_switch_en in DPLL1/2_mon_sw_pbo_cnfg register can be
used to set hitless reference switching. When a Hitless Switching (HS)
event is triggered, the phase offset of the selected input clock with
respect to the DPLL1/2 output is measured. The device then automati-
cally accounts for the measured phase offset and compensates for the
appropriate phase offset into the DPLL output so that the phase tran-
sients on the DPLL1/2 output are minimized. The input frequencies
should be set to frequencies equal to 8kHz or higher.
If hitless_switch_en is set to “1”, a HS event is triggered if any one of
the following conditions occurs:
• DPLL1/2 selected input clock switches to a different reference
• DPLL1/2 exits from Holdover mode or Free-Run mode
For the two conditions, the phase transients on the DPLL1/2 output
are minimized to be no more than 0.61 ns with HS. The HS can also be
frozen at the current phase offset by setting the hitless_switch_freeze bit
in DPLL1/2_mon_sw_pbo_cnfg register. When the HS is frozen, the
device will ignore any further HS events triggered by the above two con-
ditions, and maintain the current phase offset.
When the HS is disabled, there may be a phase shift on the DPLL1/2
output, as the DPLL1/2 output tracks back to 0 degree phase offset with
respect to the DPLL1/2 selected input clock. This phase shift can be lim-
ited; see section 3.1.2.1.8 Phase Slope Limit on page 17.
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Revision 6, July 21, 2016