82P33741 Datasheet, PDF (22/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
3.1.3.3.2 Automatic Selection
In Automatic selection, the input clock selection is determined by
input clock being valid, priority and input clock configuration. The input
clock is declared valid depending on the results of input clock quality
monitoring (refer to Chapter 3.1.3.2). The input clock can be configured
to be valid and therefore be allowed to participate in the locking process
by setting to “0” the corresponding INn_VALID bit (12  n  1) in
DPLL_remote_input_valid_cnfg register, by default all the inputs are not
valid, and therefore the user must set the corresponding bit to “0” in
order to allow the DPLL to lock to a particular input clock. Within all the
qualified input clocks, the one with the highest priority is selected. The
priority is set by the corresponding INn_SEL_PRIORITY[3:0] bits in
DPLL_INn_sel_priority_cnfg (12  n  1). If more than one qualified
input clock INn is available, then it is important to set appropriate priori-
ties to the input clocks, two input clocks must not have the same priority.
This process is shown in Figure 9.
In pu t C lo ck V a lid a tio n
P rio rity
Inp u t co n fig u ra tio n
No
No
No
In pu t C lo ck Q u ality M o n ito rin g
(L O S , A ctivity, F re q u en cy)
IN n = '1 '
IN n_S E L_P R IO R ITY [3:0]
'0 0 0 0 '
IN n _ V A L ID = '0 '
Yes
Yes
Yes
A ll q u a lifie d in p u t clo cks a re a va ila b le fo r A u to m a tic se le ction
Figure 9. Qualified Input Clocks for Automatic Selection
3.1.3.3.2.1 Input Clock Validation
For all the input clocks, the input is declared valid depending on the
results of input clock quality monitoring (refer to Chapter 3.1.3.2). The
IN_NOISE_WINDOW bit should be set to ‘1’ if any of INn_FREQ[3:0] is
set for frequencies  8 kHz, by default it is set to ‘0’.
For DPLL1 and DPLL2, the following conditions must be satisfied for
the input clock to be valid; otherwise, it is invalid.
• No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
• No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is
‘0’);
• No phase lock alarm, i.e., the INn_PH_LOCK_ALARM bit is ‘0’;
• If the ULTR_FAST_SW bit is ‘1’, the DPLL selected input clock
misses less than (<) 2 consecutive clock cycles; if the ULTR_-
FAST_SW bit is ‘0’, this condition is ignored;
• LOS[3:0] are not set to disqualify the input clock
For DPLL3, the following conditions must be satisfied for the input
clock to be valid; otherwise, it is invalid.
• No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
• No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is
‘0’);
• LOS[3:0] are not set to disqualify the input clock
The INn bit (12  n  1) indicates whether or not the clock is valid.
When the input clock changes from ‘valid’ to ‘invalid’, or from ‘invalid’ to
‘valid), the INn bit will be set. If the INn bit is ‘1’, an interrupt will be gen-
erated.
When the DPLL selected input clock has failed, i.e., the selected
input clock changes from ‘valid’ to ‘invalid’, the DPLL_MAIN_REF_-
FAILED bit will be set. If the DPLL_MAIN_REF_FAILED bit is ‘1’, an
interrupt will be generated.
3.1.3.3.2.2 Revertive and Non-Revertive Switching
For DPLL1 and DPLL2, Revertive and Non-Revertive switchings are
supported, as selected by the REVERTIVE_MODE bit.
For DPLL3, only Revertive switching is supported.
GR-1244 defines Revertive and Non-Revertive Reference switching.
In Non-Revertive switching, a switch to an alternate reference is main-
tained even after the original reference has recovered from the failure
that caused the switch. In Revertive switching, the clock switches back
to the original reference after that reference recovers from the failure,
independent of the condition of the alternate reference. In Non-Revertive
switching, input clock switch is minimized.
In Revertive switching, the selected input clock is switched when
another qualified input clock with a higher priority than the current
selected input clock is available. Therefore, if REVERTIVE_MODE bit is
set to “1”, then the selected input clock is switched if any of the following
is satisfied:
• the selected input clock is disqualified;
• another qualified input clock with a higher priority than the
selected input clock is available.
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Revision 6, July 21, 2016