82P33741 Datasheet, PDF (51/61 Pages) Integrated Circuit Systems – Differential reference inputs

Table 35: SONET/SDH Output Clock Jitter Generation
(jitter measured on one differential output of APLL3 with all other outputs disabled)
Output Frequency
RMS Jitter Typ (ps)
RMS Jitter Max (ps)
0.23
0.26
0.25
0.29
0.10
0.14
622.08 MHz
0.30
1.41
0.28
0.51
0.23
0.28
0.20
0.23
0.19
0.22
0.11
0.13
NOTE 1: DPLL locked to input clock
82P33741 Datasheet
Test Filter
12 kHz to 20 MHz
20kHz to 80 MHz
4 MHz to 80 MHz
500 Hz to 1.3 MHz
1 kHz to 5 MHz
5 kHz to 20 MHz
65 kHz to 1.3 MHz
250 kHz to 5 MHz
1 MHz to 20 MHz
Notes
GR-253-CORE and ITU-T
G.813 Option 2
limit 0.1 UI p-p /
0.01 UI RMS
(STM-16: 1UI = 0.40 ns)
GR-253-CORE and ITU-T
G.813 Option 2
limit 0.3 UI p-p
(STM-64: 1 UI = 0.10 ns)
ITU-T G.813 Option 1
limit 0.5 UI p-p
(STM-64: 1 UI = 0.10 ns)
GR-253-CORE and ITU-T
G.813 Option 2
limit 0.1 UI p-p
(STM-64: 1 UI = 0.10 ns)
ITU-T G.813 Option 1
limit 0.1 UI p-p
(STM-64: 1 UI = 0.10 ns)
ITU-T G.813 Option 1
limit 0.5 UI p-p
(STM-1: 1 UI = 6.43 ns)
ITU-T G.813 Option 1
limit 0.5 UI p-p
(STM-4: 1 UI = 1.61 ns)
ITU-T G.813 Option 1
limit 0.5 UI p-p
(STM-16: 1UI = 0.40 ns)
ITU-T G.813 Option 1
limit 0.1 UI p-p
(STM-1: 1 UI = 6.43 ns)
ITU-T G.813 Option 1
limit 0.1 UI p-p
(STM-4: 1 UI = 1.61 ns)
ITU-T G.813 Option 1
limit 0.1 UI p-p
(STM-16: 1UI = 0.40 ns)
©2016 Integrated Device Technology, Inc.
51
Revision 6, July 21, 2016