82P33741 Datasheet, PDF (40/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
8.3.2.2
LVPECL Output Port
8.3.2.2.1 LVPECL Termination for 3.3 V
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
The differential outputs are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for func-
tionality. These outputs are designed to drive 50 transmission lines.
Matched impedance techniques should be used to maximize operating
frequency and minimize signal distortion. Figure 17 and Figure 18 show
two different layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
3.3V
LVPECL
3.3V
R3
R4
125Ω
125Ω
3.3V
Z_o = 50Ω
+
Z_o = 50Ω
R1
84Ω
_
R2
84Ω
Input
Figure 17. 3.3V LVPECL Output Termination
3.3V
Z_o = 50Ω
3.3V
+
LVPECL
Z_o = 50Ω
R1
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
* Z_o
_
Input
R2
50Ω
V_CC - 2V
RTT
Figure 18. 3.3V LVPECL Output Termination
8.3.2.2.2 LVPECL Termination for 2.5 V
Figure 19 and Figure 20 show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50 to
VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground
level. The R3 in Figure 20 can be eliminated and the termination is
shown in Figure 21.
Figure 19. 2.5V LVPECL Output Termination
Figure 20. 2.5V LVPECL Output Termination
©2016 Integrated Device Technology, Inc.
Figure 21. 2.5V LVPECL Output Termination
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Revision 6, July 21, 2016