82P33741 Datasheet, PDF (43/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
8.3.4
OUTPUT CLOCK DUTY CYCLE
Table 29: Output Clock Duty Cycle (OUT1 - OUT9)
Clock Output Frequency
Min
Typ
Max
Unit
Test Condition
f_OUT<570MHz
45
f_OUT>570MHz
35
NOTE: Output Duty Cycle configured using APLL1 or APLL2.
55
%
65
%
Table 30: Output Clock Duty Cycle (OUT10 - OUT11)
Clock Output Frequency
Min
Typ
Max
Unit
Test Condition
f_OUT<600MHz
47
f_OUT>600MHz
45
53
%
55
%
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43
Revision 6, July 21, 2016