82P33741 Datasheet, PDF (48/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
Table 34: Gigabit Ethernet LAN Output Clock Jitter Generation
(jitter measured on one differential output of APLL3 with all other outputs disabled)
Output Frequency
RMS Jitter Typ (ps)
RMS Jitter Max (ps)
0.23
0.27
Test Filter
10 kHz - 20 MHz
0.25
161.1328125 MHz
0.14
0.29
20 kHz - 40 MHz
0.19
1 MHz - 30 MHz
0.09
0.12
1.875 MHz - 20 MHz
0.20
0.22
10 kHz - 1 MHz
0.23
0.26
10 kHz - 20 MHz
0.25
322.265625 MHz
0.13
0.30
20 kHz - 80 MHz
0.16
1 MHz - 30 MHz
0.07
0.10
1.875 MHz - 20 MHz
0.20
0.22
10 kHz - 1 MHz
0.23
0.27
10 kHz - 20 MHz
0.24
644.53125 MHz
0.12
0.28
20 kHz - 80 MHz
0.15
1 MHz - 30 MHz
0.07
0.09
1.875 MHz - 20 MHz
0.20
0.23
10 kHz - 1 MHz
NOTE 1: DPLL locked to input clock
NOTE 2: For BER = 10–12, RMS jitter = p-p jitter/13.8 per IEEE 802.3-2008 and IEEE 802.3ae-2002 section 48B.3.1.3.1
Notes
IDT Target Test Filter for
10GbE
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 96.97 ps)
IEEE 802.3-2008
limit 0.28 UI p-p /
0.0203 UI RMS
(1 UI = 96.97 ps)
IDT Target Test Filter for
10GbE
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 96.97 ps)
IEEE 802.3-2008
limit 0.28 UI p-p /
0.0203 UI RMS
(1 UI = 96.97 ps)
IDT Target Test Filter for
10GbE
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 96.97 ps)
IEEE 802.3-2008
limit 0.28 UI p-p /
0.0203 UI RMS
(1 UI = 96.97 ps)
©2016 Integrated Device Technology, Inc.
48
Revision 6, July 21, 2016