82P33741 Datasheet, PDF (28/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
By default, the falling edge of the frame/sync input signal is aligned
with the rising edge of the DPLL1/2 selected input clock. The rising edge
of frame/sync input signal can be set to be aligned with the rising edge
of the DPLL1/2 selected input clock by setting sync_edge bit to “1” in
DPLL1/2_sync_edge_cnfg register.
The EX_SYNC_ALARM_MON bit indicates whether frame/sync
input signal is in external sync alarm status. The external sync alarm is
indicated by the EX_SYNC_ALARM bit. If the EX_SYNC_ALARM bit is
‘1’, the occurrence of the external sync alarm will trigger an interrupt.
The 8 kHz frame pulse, the 2 kHz frame pulse, and the 1PPS sync
signal can be inverted by setting the 8K_1PPS_INV and 2K_1PPS_INV
bits of Frame Sync and Multiframe Sync Output Configuration Register.
The 8 kHz and the 2 kHz frame sync outputs can be 50:50 duty cycle
or pulsed, as determined by the 8K_PUL and 2K_PUL bits respectively.
When they are pulsed, the pulse width derived from DPLL1 is defined by
the period of OUT1, and the pulse width derived from DPLL2 is defined
by the period of an internal clock. They are pulsed on the position of the
falling or rising edge of the standard 50:50 duty cycle, as selected by the
2K_8K_PUL_POSITION bit of Frame Sync and Multiframe Sync Output
Configuration Register.
3.1.8 INPUT AND OUTPUT PHASE CONTROL
The device has several features to allow a tight control of the phase
on the input and output clocks.
3.1.8.1 DPLL1 and DPLL2 Phase offset control
The phase offset of the DPLL1/2 selected input clock with respect to
the DPLL1/2 output can be adjusted. If the device is configured as the
active PLL in a redundancy system, then the PH_OFFSET_EN bit deter-
mines whether the input-to-output phase offset is enabled. If the device
is configured as the inactive PLL in a redundancy system, then the
input-to-output phase offset is always enabled. If enabled, the input-to-
output phase offset can be adjusted by setting the PH_OFF-
SET_CNFG[28:0] bits in DPLL1/2 phase offset configuration register.
The register value is a 2's complement phase offset with a resolution of
0.0745ps and a total range of [20us, - 20us].
The input-to-output phase offset can be calculated as follows:
Phase Offset (ps) = PH_OFFSET[28:0] X 0.0745
3.1.8.2 Input Phase control
All the inputs phase can be controlled individually. They can be pro-
grammed with a resolution of 0.61 ns and a range of [77.5 ns,-78.1ns] by
setting INn_PHASE_OFFSET_CNFG[7:0] bits (1 < n < 12) in the input
phase offset configuration register. The register value is a 2's comple-
ment phase offset, the default is zero. The programmed offset is auto-
matically applied to the DPLL1 and DPLL2 when a particular input is
selected. If the manual DPLL1 and DPLL2 phase offset control is used
then the per-input phase offset is not applied.
3.1.8.3 Output Phase control
The output phase can be controlled individually for outputs OUT1 to
OUT7. There is the coarse phase control that allows the output phase to
be adjusted as low as 1.6ns. There is a fine phase adjustment that
allows the output phase to be adjusted as low as 187.27 ps. The total
range is +/-180^o.
There are two registers associated with the coarse phase adjust-
ment, the OUTn_PH1_CNFG (1 < n < 7) and the OUTn_PH2_CNFG (1
< n < 7) registers. The OUTn_PH1_CNFG register is associated with
output divider 1 as shown in Figure 10 and Figure 11, the phase can be
adjusted by a step size that is equal to the period of the input of clock of
the output Div1, the number set in the OUTn_PH1_CNFG register
should not be larger than the number set in OUTn_DIV1_CNFG register.
The OUTn_PH2_CNFG register is associated with output divider 2 as
shown in Figure 10 and Figure 11, the phase can be adjusted by a step
size that is equal to the period of the input of clock of the output Div2, the
number set in the OUTn_PH2_CNFG register should not be larger than
the number set in OUTn_DIV2_CNFG register.
There is a register that is associated with the fine phase adjustment,
the OUTn_FINE_CNFG (1 < n < 7). For the fine phase adjustment, the
output clocks must be output from the APLLs, The phase can be
adjusted by a step size that is equal to the 1/2 of the period of the VCO.
For Ethernet clocks the VCO frequency is 2.5GHz, for Ethernet LAN
PHY the VCO frequency is 2.578125 GHz, and for SONET/SDH clocks
the VCO frequency is 2.48832 GHz. OUT1 can be output from the
DPLLs, and in that case the fine phase adjustment is not available, it is
only available if the clocks are output from the APLLs.
The output phase adjustments are not available for OUT8, OUT9,
OUT10, and OUT11.
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Revision 6, July 21, 2016