82P33741 Datasheet, PDF (27/61 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 Datasheet
Table 14: Outputs on OUT10~11
OUTn_ODSEL0/1[2:0]
(Output Divider)
SONET
(XTALn =
24.8832 MHz)
Outputs on OUT10~11¹
ETHERNET
(XTALn =
25 MHz)
ETHERNET * 66/64
(XTALn =
25.78125 MHz)
1
622.08 MHz
625 MHz
644.53125 MHz
2
311.04 MHz
312.5 MHz
322.265625 MHz
4
155.52 MHz
156.25 MHz
161.1328125 MHz
5
125 MHz
8²
77.76 MHz
25³
25 MHz
(OUTn_ENABLE = 0)
Output ‘n’ is disabled
(OUTn_ENABLE = 1)
Output ‘n’ is enabled
Note:
1. The blank cell means the configuration is reserved. The proper XTAL must be populated for XTAL1~2 based on the
selected mode.
2. OUT11 only
3. OUT10 only
OUT1 to OUT9 output clocks can be inverted by setting OUTn_IN-
VERT bit (0: output not inverted, 1: output inverted) in OUTn_MUX-
_CNFG register for (1 < n < 7), and in OUT8_CNFG and OUT8_CNFG
registers for OUT8 and OUT9 respectively.
The output clocks can be squelched by setting OUT-
n_SQUELCH[1:0] bits (0x: no squelch, 10: squelch to '0', 11: squelch to
'1') in OUTn_MUX_CNFG register for (1 < n < 7), and in OUT8_CNFG
and OUT9_CNFG registers for OUT1 to OUT9 respectively.
OUT1 to OUT7 output clocks can be individually powered down by
setting OUTn_PDN bit to '1' in OUTn_MUX_CNFG register for (1 < n <
7)
OUT10 and OUT11 can be enabled or disabled by programming
OUT10_ENABLE and OUT11_ENABLE in the OUT10 and OUT11 con-
figuration registers respectively.
82P33741 provides a variety of output frequencies from 1Hz to
650MHz.
APLL1 is always enabled and the default frequency for OUT1, OUT2,
and OUT3 is respectively 25 MHz, 125 MHz, and 156.25MHz. OUT4 is
squelched by default.
By default, OUT5 to OUT7 are squelched. Set the proper registers to
set desired frequency values for OUT5 to OUT7.
DPLL3 is disabled by default, and if it is enabled, then the default fre-
quency for OUT8 and OUT9 is respectively 16.384 MHz and 2.048 MHz.
APLL1, APLL2, and the DPLLs can be configured from an external
EEPROM after reset. It can be used to set specific start up frequency
values as needed by the application.
OUT10 and OUT11 are powered down by default. APLL3 must be
configured via the I2C slave interface to set OUT10 and OUT11 fre-
quency values.
3.1.7.2 Frame Sync Signals
Either an 8 kHz or a 2 kHz frame sync, or a 1PPS sync signal are
output on the FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS pins if
enabled by the 8K_1PPS_EN and 2K_1PPS EN bits respectively. They
are CMOS outputs.
The output sync frequencies are independent of the input sync fre-
quency. The output FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS fre-
quencies are selected through the dpll1/2_fr_mfr_sync_cnfg registers.
Any supported clock frequency at the clock input can be associated
with the sync signals.
The frame sync output signals are derived from the DPLL1 and
DPLL2 output and are aligned with the output clock. They are synchro-
nized to the frame sync input signal.
The frame/sync output signals align to the first edge of the associ-
ated reference clock that occurs after the edge of the frame/sync input
signal. The frequency of the associated reference clock must be lower or
equal to the frequencies of the output clocks that requires to be aligned
with the frame/sync pulse signal.
If the frame sync input signal with respect to the DPLL1/2 selected
input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an
external sync alarm will be raised and the frame/sync input signal is dis-
abled to synchronize the frame/sync output signals. The external sync
alarm is cleared once the frame/sync input signal with respect to the
DPLL selected input clock is within the limit. If it is within the limit,
whether frame/sync input signal is enabled to synchronize the frame
sync output signal is determined by the AUTO_EXT_SYNC_EN bit and
the EXT_SYNC_EN bit.
When the frame/sync input signal is enabled to synchronize the
frame/sync output signal, it is adjusted to align itself with the DPLL
selected input clock.
©2016 Integrated Device Technology, Inc.
27
Revision 6, July 21, 2016