GMS81C5108 Datasheet, PDF (85/102 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C5108
23. SUPPLY VOLTAGE DETECTION
The GMS81C5108 has an on-chip low voltage detection
circuitry to detect the V_DD voltage. A configuration regis-
ter, SCMR, can enable or disable the low voltage detect
circuitry. This GMS81C5108 has two level detec-
tor(SVD0, SVD1). The SVD0 flag is set when the V_DD
falls below 2.2V and if the V_DD is rise above 2.2V the
SVD0 is cleared automatically. The SVD1 flag is set when
the V_DD falls below 1.7V and if this flag is set once, it is
not cleared automatically although the V_DD rises above
1.7V. It can be cleared by writing.
If the SVD1 is set, the MCU can be RESET or frozen by
the flag SVRT. In the in-circuit emulator, supply voltage
detection is not implemented and user can not experiment
with it. Therefore, after final development of user program,
this function may be experimented or evaluated.
MSB
SCMR (System
R/W R/W R/W R
Clock Mode Register)
LSB
R/W R/W R/W R/W
ADDRESS: 0F5_H
INITIAL VALUE: 00_H
SYCC[1:0] (System clock control)
00: main clock on
01: main clock on
10: sub clock on (main clock on)
11: sub clock on (main clock off)
SCS[1:0] (System clock source select)
SVD[1:0] (SVD Flag)
f_MAIN÷2 or fSUB÷2
SVD0 : set at VDD=2.2V
f_MAIN÷2³ or fSUB÷2³
SVD1 : set at VDD=1.7V
f_MAIN÷2⁴ or f_SUB÷2⁴
SVRT (System Reset Control by SVD1 Bit) ^fMAIN^{÷26 or f}SUB^÷26
0 : System reset by SVD1 Flag
1 : Don’t system reset by SVD1 Flag (Freeze)
SVEN (SVD Operation Enable Bit)
0 : SVD Operation Enable
1 : SVD Operation Disable
* The values of 1.7V and 2.2V could be changed by ±0.2V according to the process of work.
Figure 23-1 Low Voltage Detector Register
V_DD
When SVRT = 0
Internal
RESET
V_DD
Internal
RESET
V_DD
Internal
RESET
V_DD
When SVRT = 1
System
Clock
V_DD
System
Clock
65.5mS
t < 65.5mS
65.5mS
65.5mS
SVD MAX
SVD MIN
SVD MAX
SVD MIN
SVD MAX
SVD MIN
SVD MAX
SVD MIN
SVD MAX
SVD MIN
Figure 23-2 Power Fail Processor Situations
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JUNE 2001 Ver 1.0