GMS81C5108 Datasheet, PDF (37/102 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C5108
10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It con-
tains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. Power consumption can
be reduced by switching them to the low power operation
frequency clock can be easily obtained by attaching a res-
onator between the X_IN and X_OUT pin and the SX_IN and
SX_OUT pin, respectively. The system clock can also be ob-
tained from the external oscillator.
The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the periph-
eral hardware. The internal system clock can be selected
by bit2, and bit3 of the system clock mode register (SC-
MR). The registers are shown in Figure 10-2.
CPU clock
÷2
÷8
÷ 16
÷ 64
Instruction cycle time
f_MAIN = 4MHz
f_SUB = 32.768kHz
0.5 us
61 us
2.0 us
244 us
4.0 us
488 us
16.0 us
1953 us
To the peripheral block, the clock among the not-divided
original clocks, divided by 2, 4,..., up to 1024 can be pro-
vided. Peripheral clock is enabled or disabled by STOP in-
struction. The peripheral clock is controlled by clock
control register (CKCTLR). See "11. BASIC INTERVAL
TIMER" on page 43 for details.
SYCC<1>
SYCC<0>
STOP Mode
OSC Stop
X_IN
0
SX_IN
1
SLEEP Mode
** Clock is frozen by STOP or SLEEP[SMR.0] Instruction.
** Clock is released
1) by BIT overflow when previos state has been STOP mode.
2) by interrupts when previos state has been SLEEP mode.
SCS[1:0]
select clock
÷2
÷8
MUX
÷16
÷64
Internal system clock
PRESCALER
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10
÷1 ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256 ÷512 ÷1024
Peripheral clock
f_EX (Hz)
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
Frequency 4M
2M
1M
4M
period
250n 500n
1u
500K
2u
250K
4u
125K
8u
62.5K 31.25K 15.63K 7.183K 3.906K
16u
32u
64u 128u 256u
Figure 10-1 Block Diagram of Clock Generator
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JUNE 2001 Ver 1.0