GMS81C5108 Datasheet, PDF (72/102 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C5108
17.4 External Interrupt
The external interrupt on INT0, INT1 and INT2 pins are
edge triggered depending on the edge selection register
IESR (address 0D8_H) as shown in Figure 17-6.
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
INT0
INT1
INT0IF
INT0 INTERRUPT
INT1IF
INT1 INTERRUPT
INT2
INT2IF
INT2 INTERRUPT
IESR
[0D8_H]
IESR (Ext. Interrupt Edge Selection Register)
Interrupt Edge Selection Register)
Bit : 7
-
R/W R/W R/W R/W R/W R/W
6
5
4
3
2
1
0
-
INT21 INT20 INT11 INT10 INT01 INT00
INT2[1:0] (INT2 Edge Selections)
00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
ADDRESS : 0D8_H
RESET VALUE : --000000_B
INT1[1:0] (INT1 Edge Selection) INT0[1:0] (INT0 Edge Selections)
00 : Int. Disable
00 : Int. Disable
01 : Falling (1-to-0 transition)
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
11 : Both (Rising & Falling)
Example: To use as an INT0 and INT2
:
:
;**** Set port as an input port R0
LDM R0DR,#1111_1010B
;
;**** Set port as an interrupt port
LDM PMR,#0000_0101B
;
;**** Set Falling-edge Detection
LDM IESR,#0001_0001B
:
:
:
Response Time
The INT0, INT1 and INT2 edge are latched into INT0F,
INT1F and INT2F at every machine cycle. The values are
not actually polled by the circuitry until the next machine
cycle. If a request is active and conditions are right for it to
be acknowledged, a hardware subroutine call to the re-
quested service routine will be the next instruction to be
executed. The DIV itself takes twelve cycles. Thus, a max-
imum of twelve complete machine cycles elapse between
activation of an external interrupt request and the begin-
ning of execution of the first instruction of the service rou-
tine.
Interrupt response timings are shown in Figure 17-7.
Figure 17-6 External Interrupt Block Diagram
max. 12 f_OSC
8 f_OSC
Interrupt Interrupt
goes latched
active
Interrupt
processing
Interrupt
routine
Figure 17-7 Interrupt Response Timing Diagram
JUNE 2001 Ver 1.0
69