GMS81C5108 Datasheet, PDF (44/102 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C5108
Example)
:
LDM
STOP
NOP
NOP
:
CKCTLR,#0000_1111B
The Interval Timer Register CKCTLR should be initial-
ized by software in order that oscillation stabilization time
should be longer than 20ms before STOP mode.
Release the STOP mode
The exit from STOP mode is using hardware reset or exter-
nal interrupt, watch timer, SIO interrupt, key scan or timer
interrupt (EC0).
To release STOP mode, corresponding interrupt should be
enabled before STOP mode.
Specially as a clock source of Timer/Event counter, EC0
pin can release it by Timer/Event counterInterrupt re-
quest
Reset redefines all the control registers but does not change
the on-chip RAM. External interrupts allow both on-chip
RAM and Control registers to retain their values.
Start-up is performed to acquire the time for stabilizing os-
cillation. During the start-up, the internal operations are all
stopped.
Oscillator
(X_IN pin)
Internal Clock
External Interrupt
BIT Counter n n+1 n+2
Normal Operation
STOP Instruction
Executed
n+3
Stop Operation
01
FE FF
Clear
t_ST > 20ms
by software
012
Normal Operation
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Figure 10-8 STOP Mode Release Timing by External Interrupt
Oscillator
(X_IN pin)
Internal Clock
RESET
BIT Counter
STOP Instruction
Executed
n n+1 n+2 n+3
Normal Operation
n+4
Stop Operation
01
Clear
FE FF 0 1 2
t_ST > 62.5ms
Normal Operation
at 4.19MHz by hardware
1
t_ST = _{fMAIN ÷1024} x 256
Figure 10-9 STOP Mode Release Timing by RESET
JUNE 2001 Ver 1.0
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