GMS81C5108 Datasheet, PDF (57/102 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C5108
less PWM output. In Figure 12-11, the duty data is trans-
ferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle).
The bit POL0 of TM1 decides the polarity of duty cycle.
The duty value can be changed when the PWM outputs.
However the changed duty value is output after the current
period is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 12-13. As it were, the absolute duty time is not
changed in varying frequency.
Note: If the user need to change mode from the Timer1
mode to the PWM mode, the Timer1 should be
stopped firstly, and then set period and duty register
value. If user writes register values and changes
mode to PWM mode while Timer1 is in operation,
the PWM data would be different from expected
data in the beginning.
The relation of frequency and resolution is in inverse pro-
portion. Table 12-2 shows the relation of PWM frequency
vs. resolution.
PWM Period = [PWMHR[3:2]T1PPR+1] X Source Clock
PWM Duty = [PWMHR[1:0]T1PDR+1] X Source Clock
If it needed more higher frequency of PWM, it should be
reduced resolution.
Note: If the duty value and the period value are same, the
PWM output is determined by the bit POL0 (1: High,
0: Low). And if the duty value is set to “00_H”, the
PWM output is determined by the bit POL0(1: Low,
0: High). The period value must be same or more
than the duty value, and 00_H cannot be used as the
period value.
Frequency
Resolution _{T1CK[1:0] T1CK[1:0]}
=00 (250nS) =01 (500nS)
10-bit
3.9KHz
1.95KHz
9-bit
7.8KHz
3.9KHz
8-bit
15.6KHz
7.8KHz
7-bit
31.25KHz 15.6KHz
T1CK[1:0]
=10 (2uS)
0.49KHZ
0.98KHZ
1.95KHz
3.90KHz
Table 12-2 PWM Frequency vs. Resolution at 4MHz
TM1
POL
X
16BIT
0
PWME
1
CAP1
0
T1CK1
X
T1CK0
X
T1CN
X
T1ST
X
ADDRESS : 0E2_H
RESET VALUE : 00_H
PWMHR
-
-
-
-
PWM03 PWM02 PWM01 PWM00
ADDRESS : 0E5_H
RESET VALUE : ----0000_B
Bit Manipulation Not Available
X
X
X
X
Period High
PWMHR[3:2]
Duty High
X : The value “0” or “1” corresponding your operation.
T0 clock source
T1ST
0 : Stop
1 : Clear and Start
T1PPR (8-bit)
COMPARATOR
XIN
SX_IN
0X
÷1
÷2
1X
÷8
2
SCMR[1:0]
1
MUX
T1 (8-bit)
CLEAR
T1CK[1:0]
T1CN
Slave
COMPARATOR
T1PDR (8-bit)
SQ
R
POL
PWMO
[PMR.6]
R31/PWM
PWMHR[1:0]
Master
T1PDR (8-bit)
Figure 12-11 PWM Mode
54
JUNE 2001 Ver 1.0