GMS81C5108 Datasheet, PDF (84/102 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C5108
22. RESET
The GMS81C5108 have two types of reset generation pro-
cedures; one is an external reset input, the other is a watch-
dog timer reset. Table 22-1 shows on-chip hardware ini-
tialization by reset action.
On-chip Hardware
Program counter
(PC)
RAM page register (RPR)
G-flag
(G)
Operation mode
Initial Value
(FFFF_H) - (FFFE_H)
0
0
Main-frequency clock
On-chip Hardware
Peripheral clock
SVD
Control registers
Voltage Booster
Initial Value
On
Enable
Refer to Table 8-1 on page 25
Disable
Table 22-1 Initializing Internal Status by Reset Action
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin to low for at least 8 oscillator periods, within
the operating voltage range and oscillation stable, it is ap-
plied, and the internal state is initialized. After reset,
65.5ms (at 4MHz) add with 7 oscillator periods are re-
quired to start execution as shown in Figure 22-2.
Internal RAM is not affected by reset. When V_DD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
When the RESET pin input goes to high, the reset opera-
tion is released and the program execution starts at the vec-
tor address stored at FFFE_H - FFFF_H.
A connection for simple power-on-reset is shown in Figure
22-1.
V_DD
100kΩ
+
1uF
−
RESET
GND
V_DD
Mask Option
MCU
Figure 22-1 Simple Power-on-Reset Circuit
System Clock
RESET
1234567
ADDRESS
BUS
DATA
BUS
?
??
?
FFFE FFFF Start
?
? ? ? FE ADL ADH OP
Stabilization Time
t_ST = 65.5mS at 4MHz
RESET Process Step
1
t_ST = _{fMAIN ÷1024} x 256
MAIN PROGRAM
Figure 22-2 Timing Diagram after RESET
22.2 Watchdog Timer Reset
Refer to “13.2 Watch Dog Timer” on page 57.
JUNE 2001 Ver 1.0
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