GMS81C5108 Datasheet, PDF (68/102 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C5108
17. INTERRUPTS
The GMS81C5108 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flag
(IRQH, IRQL), Interrupt Edge Selection Register (IESR),
priority circuit and Master enable flag (“I” flag of PSW).
The configuration of interrupt circuit is shown in Figure
17-1 and Interrupt priority is shown in Table 17-1 .
The flags that actually generate these interrupts are bit
INT0F, INT1F and INT2F in Register IRQH. When an ex-
ternal interrupt is generated, the flag that generated it is
cleared by the hardware when the service routine is vec-
tored to only if the interrupt was transition-activated.
The Timer 0 and Timer 2 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective tim-
er/counter register. The AD converter Interrupt is generat-
ed by ADIF which is set by finishing the analog to digital
conversion. The Basic Interval Timer Interrupt is generat-
ed by BITIF which is set by overflow of the Basic Interval
Timer Register (BITR).
Reset/Interrupt Symbol Priority Vector Addr.
Hardware Reset RESET
-
Key Scan Interrupt KS
1
BIT Interrupt
BIT
2
External Interrupt 0 INT0
3
External Interrupt 1 INT1
4
Timer 0 Interrupt
T0
5
Timer 1 Interrupt
T1
6
External Interrupt 2 INT2
7
Remocon Interrupt REM
8
AD Interrupt
AD
9
SIO Interrupt
SIO
10
Watch Timer Interrupt WT
11
FFFE_H
FFFC_H
FFFA_H
FFF8_H
FFF6_H
FFF4_H
FFF2_H
FFF0_H
FFEE_H
FFEC_H
FFEA_H
FFE8_H
Table 17-1 Interrupt Priority
Internal bus line
Ext. Int. 0
Ext. Int. 1
Ext. Int. 2
IRQH
Key Scan
BIT
IESR _{Timer 0}
Timer 1
6
KSIF
5
BITIF
INT0IF ⁴
INT1IF ³
TOIF ²
T1IF ¹
INT2IF ⁰
IENH
Remocon
A/D Converter
SIO
WT
REMIF ⁶
5
ADIF
4
SIOIF
3
WTIF
Interrupt Enable
Register (Higher byte)
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
Release STOP
I Flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
To CPU
IRQL
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 17-1 Block Diagram of Interrupt Function
JUNE 2001 Ver 1.0
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