GMS81C5108 Datasheet, PDF (59/102 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C5108
13. Watch Timer/Watch Dog Timer
This has two functions, one is the interrupt occurrence for
watch time and the other is the signal generation of
13.1 Watch Timer
The watch timer consists of the clock selector, 21-bit bina-
ry counter and watch timer mode register. It is a multi-pur-
pose timer. It is generally used for watch design.
The bit 1,2 of WTMR select the clock source of watch tim-
er among sub-clock, f_MAIN÷2⁷ of main-clock and f_MAIN of
main-clock. The f_MAIN of main-clock is used usually for
watch timer test, so generally it is not used for the clock
source of watch timer. The f_MAIN÷2⁷ of main-clock is used
when the single clock system is organized. In f_MAIN÷2⁷
WDTOUTB for watch dog.
clock source, if the CPU enters into stop mode, the main-
clock is stopped and then watch timer is also stopped. If the
sub-clock is the source clock, the watch timer count cannot
be stopped. Therefore, the sub-clock does not stop but con-
tinues to oscillate even when the CPU is in the STOP
mode. The timer counter consists of 21-bit binary counter
and it can count to max 64 seconds at sub-clock.
The bit 2, 3 of WTMR select the interrupt request interval
of watch timer among 2Hz, 4Hz, 16Hz and 1/64Hz.
WTMR (Watch Timer Mode Register)
R/W R/W R/W R/W R/W R/W R/W
Bit :
7
6
5
4
3
2
1
0
-
WTEN
WDTEN WDTCL
WTIN1
WTIN0
WTCK1 WTCK0
ADDRESS: 0EF_H
INITIAL VALUE:-0000000_B
WTEN (Watch Timer Enable Bit)
0: Watch Timer Disable
1: Watch Timer Enable
WDTEN (Watch Dog Timer Enable Bit)
0: Watch Dog Timer Disable
1: Watch Dog Timer Enable
WDTCL (Watch Dog Timer Clear Bit)
0: Timer running
1: WDT Clear (Auto reset after 1 cycle)
WTCK[1:0] (Watch Timer Clock Source Selection)
00: Sub. Clock (f_SUB)
01: Main Clock (f_MAIN÷2⁷)
10: Main Clock (f_MAIN)
11: -
WTIN[1:0] (Watch Timer Interrupt Interval Selection)
00: 16Hz
01: 4Hz
10: 2Hz
11: 1/64Hz
* When f_SUB = 32.768 kHz and f_MAIN = 4.19 MHz
Figure 13-1 Watch Timer Mode Register
WTCK[1:0]
f_SUB
f_MAIN÷2⁷
f_MAIN
MUX
21 BIT
Binary Counter
WTEN
WDTCL
WTIN[1:0]
16 Hz
4 Hz
2 Hz
1/64 Hz
MUX
2 Bit
F/F
WDTEN
Watch Timer
Interrupt
WTIF
WDTOUT
Figure 13-2 Watch Timer Block Diagram
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JUNE 2001 Ver 1.0