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MB86R01 Datasheet, PDF (9/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET | |||
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MB86R01 DATA SHEET
AHB1 bus
Following resources are connected.
⢠CPU core: Bus masters of instruction (I)/data (D)
⢠GDC: GDC register part
⢠AHB2AXI: AXI port for main memory access
⢠CCPB: Encrypted ROM decoding block
⢠External BUS I/F: External bus interface (connected through CCPB)
⢠SRAM: General purpose internal SRAM 32KB à 2
⢠DMAC: General purpose DMA à 8ch
It operates as bus master at data transfer
⢠Boot ROM: Built-in boot ROM
⢠I2S_0/1/2: Serial audio controller à 3ch
⢠USB 2.0 Function DMAC: USB function DMAC
It operates as bus master at data transfer
⢠USB2.0 Host: It operates as USB2.0 EHCI, USB1.1 OHCI bus masters
⢠IDE66/IDE66DMAC: Register part of IDE host controller and built-in DMAC
The DMAC part operates as bus master at data transfer
⢠MLB: MediaLB controller
⢠AHB2
⢠APBBRG0/1/2: AHB-APB bridge circuit à 3ch
AHB2 bus
⢠CCPB: Encrypted ROM decoding block
⢠USB 2.0 Function: USB 2.0 function controller's register part
⢠USB 2.0 Host: USB 2.0 host controller's register part
⢠SDMC: SD memory controller
⢠DDR2 controller: DDR2 controller's register part
APB_TOP_0
This block bridges between APBBRG0 bus and AHB1 bus, and following low-speed peripheral resources
are connected.
⢠Interrupt controller (IRC) à 2ch
⢠External interrupt controller (EXTIRC)
⢠Clock reset generator (CRG)
⢠UART (ch0 and ch1) à 2ch
⢠Remap boot controller (RBC)
⢠32 bit general-purpose timer (32 bit timer) à 2ch
APB_TOP_1
This block bridges between APBBRG1 bus and AHB1 bus, and following low-speed peripheral resources
are connected.
⢠I2C controller à 2ch
⢠CAN controller à 2ch
⢠UART (ch2 and ch3) à 2ch
⢠A/D converter (ADC) à 2ch
APB_TOP_2
This block bridges between APBBRG2 bus and AHB1 bus, and following low-speed peripheral resources
are connected.
⢠PWM controller (PWM)
⢠SPI controller (SPI)
⢠CCNT
⢠UART (ch4 and ch5) à 2ch
FUJITSU MICROELECTRONICS
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PROPRIETARY AND CONFIDENTIAL
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