MB86R01 Datasheet, PDF (84/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET

MB86R01 DATA SHEET
8.5.14.2. IDE Ultra DMA Timing
Table 8-51 AC timing of Ultra DMA
Value
Symbol
Description
mode0
mode1
mode2
mode3
mode4 Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
T2cycleTYP
Typical sustained average 2 cycle
time
240 – 160 – 120 – 90 – 60 – ns
T2cycle
2 cycle time allowing for clock
variations (from rising edge to next
rising edge or from falling edge to
230
–
154
–
115
–
86
–
57
–
ns
next falling edge of STROBE)
Tcycle
Cycle time allowing for asymmetry
and clock variations (from STROBE 112 – 73 – 54 – 39 – 25 – ns
edge to STROBE edge)
Tdvs
Data valid setup time at sender (from
data valid until STROBE edge)
70
–
48
–
30
–
20
–
6.7
–
ns
Tdvh
Data valid setup time at sender (from
STROBE edge until data may
6.2 – 6.2 – 6.2 – 6.2 – 6.2 – ns
become invalid)
First STROBE time (for device to
Tfs
first negateDSTROBE from STOP – 230 – 200 – 170 – 130 – 120 ns
during data in Burst)
Tli
Limited interlock time
0 150 0 150 0 150 0 100 0 100 ns
Tmli
Interlock time with minimum
20 – 20 – 20 – 20 – 20 – ns
Tui
Unlimited interlock time
0 – 0 – 0 – 0 – 0 – ns
Maximum time allowed for output
Taz
drivers to release (from asserted or – 10 – 10 – 10 – 10 – 10 ns
negated)
Tzah
Minimum delay time required for
output
20 – 20 – 20 – 20 – 20 – ns
Tzad
Drivers to assert or negate (from
released)
0 – 0 – 0 – 0 – 0 – ns
Tenv
Envelope time (from DMACK- to
STOP and HDMARDY- during data
in burst initiation and from
20 70 20 70 20 70 20 55 20 55 ns
IDE_XDDDMACK to STOP during
data out burst initiation)
Ready-to-final-STROBE time (no
Trfs
STROBE edges shall be sent this
– 75 – 70 – 60 – 60 – 60 ns
long after negation of DMARDY)
Trp
Minimum time to assert STOP or
negate IDE_DMARQ
160 – 125 – 100 – 100 – 100 – ns
Tiordyz
Maximum time before releasing
IDE_DIORDY
– 20 – 20 – 20 – 20 – 20 ns
tziordy
Minimum time before driving
STROBE
0 – 0 – 0 – 0 – 0 – ns
Tack
Setup and hold times for DMACK-
(before assertion or negation)
20
–
20
–
20
–
20
–
20
–
ns
Time from STROBE edge to
Tss
negation of DMARQ or assertion of 50 – 50 – 50 – 50 – 50 – ns
STOP (when sender terminates burst)
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