MB86R01 Datasheet, PDF (8/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET

MB86R01 DATA SHEET
• I2S is addable up to 3ch
• The number of UART channel is extensible up to 6ch
• The data width in the external bus interface is extensible to 32 bit
3. Block diagram
Figure 3-1 shows block diagram of MB86R01.
JTAG_SEL
Chip_JTAG
JTAG IF
I-Cache
16KB
ETM9CSSingle
I-TCM
16KB
DDR2 Controller
AHB2AXI
HBUS2AXI
MBUS2AXI
MBUS2AXI
External
BUS I/F
D-Cache
16KB
I
D
D-TCM
16KB
HOST IF
DRAW & GEO
DISP
DISP
CAP
CAP
CCPB
S1-05
SRAM
32KB
S1-08
SRAM
32KB
DMAC
8ch
M1-2
S1-01
S1-02
M1-0
M1-1
BOOT
ROM
32KB
S1-04
I2S_0
I2S_1
I2S_2
S1-13
S1-14
S1-10
S1-03
S1-11
S2-00
S1-00
M1-5
USB2.0
Function
DMAC
M1-8
M1-4
USB2.0
Function
PHY
Wrapper
S2-03
USB2.0
Host
Wrapper
S2-02
SDMC
S2-01
M1-6
IDE66
DMAC
S1-07
IDE66
S1-06
S1-15
S1-12
M1-7
S2-04
M2-0
MediaLB
S1-09
Slave No.
Master No.
IRC
×IR2C
EXTIRC
4ch
CRG
UART
×UA2RT
GPIO
24ch
RBC
×4
32bit
Timer
2ch
I2C
×I22C
×2
CAN
×C2AN
×2
UART
×P2WM
×2
ADC
×A2DC
×4
PWM
2ch
SPI
×1
CCNT
UART
×UA2RT
×4
Figure 3-1 Block diagram of MB86R01
CPU core
This is CPU core block of ARM926EJ-S which is connected to each I/O through AHB bus in LSI.
Instruction (I)/Data (D) function as a separate bus master for Harvard architecture.
GDC_TOP
This is MB86296 compatible GDC which has 2 functions: AHB slave function writes required display list
for drawing to GDC with having CPU or DMA controller as master, and AXI master function reads display
list arranged in DDR2 memory with having GDC as master.
AXI bus
This bus bridges main memory and internal resource. Following four bus masters are connected.
• AHB1: Each bus master of AHB bus such as CPU and DMA controller
• HBUS: HOST IF on GDC
• DRAW & GEO: Draw (2D/3D drawing) and GEO (geometry engine) on GDC
• MBUS: DISP (display controller) and CAP (Video capture) on GDC
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