MB86R01 Datasheet, PDF (50/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET

MB86R01 DATA SHEET
8.4.2. DDR2SDRAM IF I/O (SSTL_18)
SSTL_18 DC characteristics (excerpted from JESD8-15a).
Table 8-8 SSTL18 Input DC Logic Levels (Single Ended)
Symbol
Parameter
Min.
VIH (DC)
DC input logic High
VREF + 125
VIL (DC)
DC input logic Low
-300
Max.
Unit
VDDQ + 300
mV
VREF - 125
mV
Table 8-9 SSTL18 Input AC Logic Levels (Single Ended)
Symbol
Parameter
Min.
VIH (AC)
AC input logic High
VREF + 250
VIL (AC)
AC input logic Low
–
Max.
Unit
–
mV
VREF - 250
mV
Table 8-10 SSTL18 Input AC Test Conditions (Single Ended)
Symbol
Condition
VREF
Input reference voltage
VSWING (max.) Input single maximum peak to peak swing
SLEW
Input single minimum slew rate
Value
0.5 × VDDQ
1.0
1.0
Unit
V
V
V/ns
Table 8-11 SSTL18 Input DC Logic Levels (Differential Ended)
Symbol
Parameter
Min.
VIN (DC)
DC input signal voltage
-300
VID (DC)
DC differential input voltage
250
Max.
Unit
VDDQ + 300
mV
VDDQ + 600
mV
Table 8-12 SSTL18 Input AC Logic Levels (Differential Ended)
Symbol
Parameter
Min.
Max.
Unit
VID (AC)
AC differential input voltage
500
VDDQ + 600
mV
VIX (AC)
AC differential cross point voltage
0.5 × VDDQ - 175 0.5 × VDDQ + 175 mV
Table 8-13 SSTL18 Input AC Test Conditions (Differential Ended)
Symbol
Parameter
Min.
Max.
Vr
Input timing measurement reference
level
VIX (cross point)
VSWING
Input signal peak to peak swing
voltage
–
1.0
SLEW
Input signal slew rate
1.0
–
Unit
V
V
V/ns
Table 8-14 SSTL18 Output DC Current Drive
Symbol
Parameter
Min.
IOH (DC)
Output minimum source DC current
-11.4 (*3)
IOL (DC)
Output minimum sink DC current
11.4 (*3)
*1: VDDQ = 1.7V, VOUT = 1420mV
*2: VDDQ = 1.7V, VOUT = 280mV
*3: The value is different from JESD8-15a. (JESD8-15a: ±13.4mA)
Max.
–
–
Unit Notes
mA (*1)
mA (*2)
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