MB86R01 Datasheet, PDF (77/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET

MB86R01 DATA SHEET
8.5.12. MediaLB Signal Timing
8.5.12.1. MediaLB AC Spec Type A
Ground = 0V; Load capacitance = 60pF; MediaLB speed = 256Fs or 512Fs; Fs = 48kHz; all timing
parameters specified from the valid voltage threshold as listed below; unless otherwise noted.
8.5.12.1.1. Clock
Table 8-40 AC Timing of Clock Signal
Signal
Symbol
Description
Value
Unit
Min. Typ. Max.
Comment
f_mck
MLBCLK operating frequency
(*1)
11.264 –
–
256xFs at 44.0kHz
– 22.5792 – MHz 512xFs at 44.1kHz
–
– 24.6272
512xFs at 48.1kHz
t_mckr MLBCLK rising time
–
–
3
ns V_IL to V_IH
MLBCLK
t_mckf
t_mckc
MLBCLK falling time
MLBCLK cycle time
–
–
3
ns V_IH to V_IL
–
–
81
40
–
–
ns
256xFs
512xFs
t_mckl MLBCLK low time
30
37
14
17
–
–
ns
256xFs
512xFs
t_mckh MLBCLK high time
30
38
14
17
–
–
ns
256xFs
512xFs
t_mpwv MLBCLK pulse width variation
–
–
2 ns pp (*2)
*1: The controller can shut off MLBCLK to place MediaLB in a low-power state.
*2: Pulse width variation is measured at 1.25V by triggering on one edge of MLBCLK and measuring the spread on the
other edge, measured in ns peak-to-peak (pp).
8.5.12.1.2. Input Signal
Table 8-41 AC Timing of Input Signal
Signal
Symbol
Description
MLBSIG, MLBDAT
input
t_dsmcf
t_dhmcf
MLBSIG and MLBDAT input
valid to MLBCLK falling
MLBSIG and MLBDAT input
hold
from MLBCLK low
Min.
4
Value
Typ.
–
Unit
Max.
– ns
Comment
0
–
– ns
8.5.12.1.3. Output Signal
Table 8-42 AC Timing of Output Signal
Signal
Symbol
Description
Value
Unit
Min. Typ. Max.
Comment
MLBSIG and MLBDAT output
MLBSIG, MLBDAT ^tmcfdz ^{high impedance from MLBCLK}
0
output
low
–
t_mckl ns
t_mdzh Bus hold time
4
–
– ns (*1)
*1: The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven
bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
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PROPRIETARY AND CONFIDENTIAL