MB86R01 Datasheet, PDF (44/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET

MB86R01 DATA SHEET
8.3. Precautions at Power On
8.3.1. Recommended Power On/Off Sequence
Follow the power on/off sequence as shown below:
<ON>: VDDI (internal and PLLVDD) → DDRVDE (external) → VDDE (external) → Signal
<OFF>: Signal → VDDE (external) → DDRVDE (external) → VDDI (internal and PLLVDD)
VDDI
VDDE
DDRVDE
Figure 8-1 Recommended Power On/Off Sequence (1)
There is no limitation on the sequence of power on/off of VDDI, VDDE, and DDRVDE if the following
condition is met. (Figure 8-2)
• Do not apply VDDE and DDRVDE (external) continuously more than 1 second when VDDI (internal)
is off.
VDDI
VDDE
DDRVDE
1 sec. or less
1 sec. or less
Figure 8-2 Recommended Power On/Off Sequence (2)
Perform power on/off for VREF according to the DDR2-SDRAM regulation.
Perform power on/off so that power for PLLVDD (PLL) does not exceed VDDI.
Turn on all power. Turning on only a part of them is prohibited.
CMOS IC becomes unstable immediately after power-on so that proceed reset immediately.
Set the reset pins (XTRST and XRST) to Low when power-on.
Input clock to CLK pin immediately after power-on.
It requires at least 100 clocks (input clock to CLK pin) for the reset signal "L" applied to the XRST pin to
be transmitted to all internal circuits.
FUJITSU MICROELECTRONICS
38
PROPRIETARY AND CONFIDENTIAL