MB86R01 Datasheet, PDF (71/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET

MB86R01 DATA SHEET
8.5.7. I2S Signal Timing
Table 8-34 Timing Requirements
Signal Symbol
Description
t_scyc
Operating frequency, I2S_SCKx (slave Mode)
I2S_SCKx _tshw
Pulse duration, I2S_SCKx High (slave Mode)
t_slw
Pulse duration, I2S_SCKx Low (slave Mode)
t_sfi
I2S_WSx
t_hfi
Setup time, external I2S_WSx High before I2S_SCKx
Low
(slave mode)
Hold time, external I2S_WSx High after I2S_SCKx
Low
(slave Mode)
t_sdi
I2S_SDIx
t_hdi
Setup time, I2S_SDIx valid before I2S_SCKx Low
(master mode)
Setup time, I2S_SDIx valid before I2S_SCKx Low
(slave Mode)
Hold time, I2S_SDIx valid after I2S_SCKx Low
(master mode)
Hold time, I2S_SDIx valid after I2S_SCKx Low (slave
mode)
B indicates AHB bus clock frequency.
T indicates I2S_SCKx cycle.
Min.
–
0.45*T
0.45*T
8
4
8
8
4
4
Value
Typ.
–
–
–
–
–
–
–
–
–
Unit
Max.
0.5*B MHz
0.55*T ns
0.55*T ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
Table 8-35 Switching Characteristics
Signal Symbol
Description
Min.
t_mcyc
Operating frequency, I2S_SCKx (master mode)
–
I2S_SCKx _tmhw
Pulse duration, I2S_SCKx high (master mode)
0.45*T
t_mlw
Pulse duration, I2S_SCKx low (master mode)
0.45*T
I2S_WSx t_dfs
Delay time, I2S_SCKx High to I2S_WSx transition
(master mode)
-12
t_ddo
I2S_SDOx
Delay time, I2S_SCKx High to I2S_SDOx valid except
the first bit of transmit frame. (master mode)
-12
Delay time, I2S_SCKx high to I2S_SDOx valid except
the first bit of transmit frame. (slave mode)
3
Delay time, I2S_SCKx high to the first bit of a transmit
t_dfb1
frame when FSPH bit of I2Sx_CNTREG register is 1. -14
(master mode)
B indicates AHB bus clock frequency.
T indicates I2S_SCKx cycle.
Value
Typ.
–
–
–
–
–
–
–
Unit
Max.
0.5*B MHz
0.55*T ns
0.55*T ns
12
ns
17
ns
32
ns
17
ns
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