MB86R01 Datasheet, PDF (66/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET

MB86R01 DATA SHEET
8.5.5. GDC Display Signal Timing
8.5.5.1. Clock
Table 8-28 AC timing of Video Interface Clock Signal
Signal
Symbol
Description
Min.
Value
Typ.
Unit
Max.
Fdclki0 DCLKI frequency
–
–
80
MHz
DCLKI0
Thdclki0 DCLKI H width
5
–
–
ns
Tldclki0 DCLKI L width
5
–
–
ns
Fdclki1 DCLKI frequency
–
–
80
MHz
DCLKI1
Thdclki1 DCLKI H width
5
–
–
ns
Tldclki1 DCLKI L width
5
–
–
ns
DCLK (internal) Tldclk0 DCLK frequency (*1)
–
–
80
MHz
DCLK (internal) Tldclk1 DCLK frequency (*1)
–
–
80
MHz
DCLKO0
Fdclko DCLKO frequency
–
–
80
MHz
DCLKO1
Fdclko DCLKO frequency
–
–
80
MHz
*1: Internal display clock of PLL synchronization mode is generated by division of internal PLL in the display clock
prescaler.
*2: DCLKI or internal display clock of PLL is output.
8.5.5.2. Input Signal
1) Applied the signal only in PLL synchronization mode (CKS = 0)
(Reference clock = Clock output from internal PLL)
Table 8-29 AC Timing of Video Interface Input Signal (1)
Signal
HSYNC0 (i)
HSYNC1 (i)
VSYNC0 (i)
VSYNC1 (i)
Symbol
Description
Twhsync0 HSYNC input pulse width
Twvsync1 VSYNC input pulse width
Twvsync VSYNC input pulse width
Twvsync VSYNC input pulse width
Min.
3.0
3.0
1
1
Value
Typ.
–
–
–
–
Max.
–
–
–
–
Unit
Clock
Clock
HSYNC
HSYNC
2) Applied the signal only in DCLKI synchronization mode (CKS = 1)
(Reference clock = DCLKI)
Table 8-30 AC Timing of Video Interface Input Signal (2)
Signal
Symbol
Description
HSYNC0 (i)
HSYNC1 (i)
VSYNC0 (i)
VSYNC1 (i)
Twhsync0 HSYNC input pulse width
Tshsync0 HSYNC Input setup time
Thhsync0 HSYNC Input hold time
Twhsync1 HSYNC input pulse width
Tshsync1 HSYNC Input setup time
Thhsync1 HSYNC Input hold time
Twvsync0 VSYNC input pulse width
Twvsync1 VSYNC input pulse width
Min.
3.0
6.0
1.0
3.0
6.0
1.0
1
1
Value
Typ.
–
–
–
–
–
–
–
–
Max.
–
–
–
–
–
–
–
–
Unit
Clock
ns
ns
Clock
ns
ns
HSYNC
HSYNC
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