MB86R01 Datasheet, PDF (60/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET

MB86R01 DATA SHEET
8.5.2. DDR2SDRAM IF
This is able to connect with DDR2 SDRAM which is in conformance with DDR2-400 in the JEDEC
(JESD79-2C.) Timing regulation is described below, and output load condition is according to the PCB
design guideline.
Table 8-22 Write Spec (1 and 2): CK-CMD/ADD and CK-DQS
Criteria value (*1)
Item
Symbol
Spec formula
Unit
Min. Typ. Max.
CMD/ADD setup valid-data from CK↑ tVD_setup_CMD (tCK/2) - 828
2172
–
–
ps
CMD/ADD hold valid-data from CK↑ tVD_hold_CMD (tCK/2) - 545
2455
–
–
ps
Skew between DQS↑ vs. CK↑
tSkew_DQS_CK Not tCK dependent -1083
–
772 Ps
*1: Spec for tck = 6ns (333Mbps) is indicated
Table 8-23 Write Spec (3): DQ-DQS
Item
Symbol
Spec formula
DQ/DM setup valid-data from DQS
tVD_setup_DQ
DQ/DM hold valid-data from DQS
tVD_hold_DQ
*1: Spec for tck = 6ns (333Mbps) is indicated
（tCK/4) - 884
（tCK/4) - 776
Criteria value (*1)
Unit
Min. Typ. Max.
616
–
–
ps
724
–
–
ps
Table 8-24 Read Spec (1): DQ-DQS
Item
Symbol
Spec formula
Criteria value (*1)
Unit
Min. Typ. Max.
tSETUP DQ from DQS
tSETUP_DQ - (0.1875*tCK – 208 ) -917
–
–
ps
tHOLD DQ from DQS
tHOLD_DQ 0.1875*tCK + 503
1628
–
–
Ps
*1: Spec for tck = 6ns (333Mbps) is indicated
Table 8-25 Read Spec (2): DQ-R.T.T (RoundTrip Time)
Item
Symbol
Spec formula
DQS RoundTripTime @CL = 3
(CK_out DRAM DQS_in)
tRTT_DQS
<Max.> 1112
<Min.> -595
*1: Spec for tck = 6ns (333Mpbs) is indicated
*2: Spec shows total delay value including tDQSCK delay of DRAM
Criteria value (*1)
Unit
Min. Typ. Max.
-355
–
+1426 ps
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