MB86R01 Datasheet, PDF (82/89 Pages) Fujitsu Component Limited. – MB86R01 DATA SHEET

MB86R01 DATA SHEET
8.5.14. IDE66 Signal Timing
8.5.14.1. IDE PIO Timing
Table 8-49 AC timing of Register Access
Symbol
Description
Value
Unit
mode0 mode1 mode2 mode3 mode4
t0
Cycle time (min.)
600
383
330
180
120 ns
t1
Address valid to IDE_XDIOR/IDE_XDIOW
setup (min.)
70
50
30
30
25
ns
t2
IDE_XDIOR/IDE_XDIOW pulse width 8 bit
(min.)
290
290
290
80
70
ns
t2i
IDE_XDIOR/IDE_XDIOW recovery time
(min.)
–
–
–
70
25
ns
t3
IDE_XDIOW data setup (min.)
60
45
30
30
20
ns
t4
IDE_XDIOW data hold (min.)
30
20
15
10
10
ns
t5
IDE_XDIOR data setup (min.)
50
35
20
20
20
ns
t6
IDE_XDIOR data hold (min.)
5
5
5
5
5
ns
t6Z
IDE_XDIOR data tristate (max.)
30
30
30
30
30
ns
t9
IDE_XDIOR/IDE_XDIOW to address valid
hold (min.)
20
15
10
10
10
ns
tRD
Read data valid to IDE_DIORDY active (if
IDE_DIORDY initially low after tA) (min.)
0
0
0
0
0
ns
tA
IDE_DIORDY setup time
35
35
35
35
35
ns
tB
IDE_DIORDY pulse width (max.)
1250 1250 1250 1250 1250 ns
tC
IDE_DIORDY assertion to release (max.)
5
5
5
5
5
ns
Table 8-50 AC timing of Data Access
Symbol
Description
Value
Unit
mode0 mode1 mode2 mode3 mode4
t0
Cycle time (min.)
600
383
240
180
120 ns
t1
Address valid to IDE_XDIOR/IDE_XDIOW
setup (min.)
70
50
30
30
25
ns
t2
IDE_XDIOR/IDE_XDIOW pulse width 8 bit
(min.)
165
125
100
80
70
ns
t2i
IDE_XDIOR/IDE_XDIOW recovery time
(min.)
–
–
–
70
25
ns
t3
IDE_XDIOW data setup (min.)
60
45
30
30
20
ns
t4
IDE_XDIOW data hold (min.)
30
20
15
10
10
ns
t5
IDE_XDIOR data setup (min.)
50
35
20
20
20
ns
t6
IDE_XDIOR data hold (min.)
5
5
5
5
5
ns
t6Z
IDE_XDIOR data tristate (max.)
30
30
30
30
30
ns
t9
IDE_XDIOR/IDE_XDIOW to address valid
hold (min.)
20
15
10
10
10
ns
tRD
Read data valid to IDE_DIORDY active (if
IDE_DIORDY initially low after tA) (min.)
0
0
0
0
0
ns
tA
IDE_DIORDY setup time
35
35
35
35
35
ns
tB
IDE_DIORDY pulse width (max.)
1250 1250 1250 1250 1250 ns
tC
IDE_DIORDY assertion to release (max.)
5
5
5
5
5
ns
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