MB84VD23381FJ Datasheet, PDF (7/54 Pages) Fujitsu Component Limited. – Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

MB84VD23381FJ-80
s DEVICE BUS OPERATIONS
User Bus Operations
Operation *^1, *²
CEf CE1r CE2r OE WE LB UB DQ7 to DQ0 DQ15 to DQ8 RESET WP/ACC*⁷
Full Standby
H H H X X X X High-Z High-Z
H
X
H L X H H X X High-Z High-Z
Output Disable *³
H
X
L H X H H X X High-Z High-Z
Read from Flash *⁴
L H X LHX X
DOUT
DOUT
H
X
Write to Flash
L H X HLXX
DIN
DIN
H
X
Read from FCRAM *⁵ H L H L H X X
DOUT
DOUT
H
X
LL
DIN
DIN
Write to FCRAM
H L H H L H L High-Z
DIN
H
X
LH
DIN
High-Z
Temporary Sector
Group
X X X XXXX
X
Unprotection *⁶
X
VID
X
Flash Hardware
Reset
X H H X X X X High-Z High-Z
L
X
Boot Block Sector
Write Protection
X X X XXXX
X
X
X
L
FCRAM Power Down*⁸ X X L X X X X
X
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1: Other operations except for this indicated table are prohibited.
*2: Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once.
*3: FCRAM Output Disable condition should not be kept longer than 1 µs.
*4: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*5: FCRAM Byte control at Read operation is not supported.
*6: It is also used for the extended sector group protections.
*7: Protect “outermost” 2 × 8 Kbytes (4 words) on both ends of the boot block sectors.
*8: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
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