MB84VD23381FJ Datasheet, PDF (22/54 Pages) Fujitsu Component Limited. – Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

MB84VD23381FJ-80
2. AC Characteristics
• Read Only Operations Characteristics (Flash)
Parameter
Symbol
JEDEC Standard
Condition
Read Cycle Time
tAVAV
tRC
—
Address to Output Delay
tAVQV
tACC
CEf = VIL
OE = VIL
Chip Enable to Output Delay
tELQV
tCEf
OE = VIL
Output Enable to Output Delay
tGLQV
tOE
—
Chip Enable to Output High-Z
tEHQZ
tDF
—
Output Enable to Output High-Z
tGHQZ
tDF
—
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
tOH
—
RESET Pin Low to Read Mode
—
tREADY
—
*: Test Conditions–Output Load : 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCf
Timing measurement reference level
Input: 0.5×VCCf
Output: 0.5×VCCf
Value*
Unit
Min
Max
70
—
ns
—
70
ns
—
70
ns
—
30
ns
—
25
ns
—
25
ns
0
—
ns
—
20
µs
21