MB84VD23381FJ Datasheet, PDF (49/54 Pages) Fujitsu Component Limited. – Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

MB84VD23381FJ-80
s DATA RETENTION CHARACTERISTICS (FCRAM)
Parameter
VCCr Data Retention Supply Voltage
VCCr Data Retention Supply Current
Data Retention Setup Time
Data Retention Recovery Time
VCCr Voltage Transition Time
*: 2.0 V ≤ VIH ≤ VCCr + 0.3 V
• Data Retention Timing (FCRAM)
Symbol
Conditions
VDR
IDR
IDR1
tDRS
tDRR
∆V/∆t
CE1r = CE2r ≥ VCCr − 0.2 V or,
CE1r = CE2r = VIH,
2.3 V ≤ VCCr ≤ 2.7 V,
VIN = VIH*or VIL,
CE1r = CE2r = VIH*, IOUT = 0 mA
2.3 V ≤ VCCr ≤ 2.7 V,
VIN ≤ 0.2 V or VIN ≥ VCCr − 0.2 V,
CE1r = CE2r ≥ VCCr − 0.2 V,
IOUT = 0 mA
2.7 V ≤ VCCr ≤ 3.1 V
at data retention entry
2.7 V ≤ VCCr ≤ 3.1 V
after data retention
Value
Unit
Min Max
2.1
3.1
V

1
mA

70
µA
0

ns
90

ns
0.5
 V/µs
3.1 V
2.7 V
VCCr
tDRS
∆V/∆t
tDRR
∆V/∆t
CE2r
2.1 V
CE1r
CE1r= CE2r > VCCr-0.2 V or
VIH* Min
0.4 V
VSS
Data Retention Mode
Data bus must be in High-Z at data retention entry.
*: 2.0 V ≤ VIH ≤ VCCr + 0.3 V
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