MB84VD23381FJ Datasheet, PDF (21/54 Pages) Fujitsu Component Limited. – Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

MB84VD23381FJ-80
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*1: This command is valid while Fast Mode.
*2: This command is valid while RESET = VID.
*3: This command is valid while HiddenROM mode.
*4: The data “00h” is also acceptable.
Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA),
Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA).
• Bus operations are defined in s DEVICE BUS OPERATION.
• RA = Address of the memory location to be read
PA = Address of the memory location to be programmed Addresses are latched on the falling edge
of the write pulse.
SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13,
and A12 will uniquely select any sector.
BA = Bank Address (A21, A20, A19)
• RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
• SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0,
0, 0, 1, 0).
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
• HRA = Address of the HiddenROM area: 000000h to 00007Fh
• HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL)
• The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• Command combinations not described in “Flash Memory Command Definitions” are illegal.
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