MB84VD23381FJ Datasheet, PDF (6/54 Pages) Fujitsu Component Limited. – Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

MB84VD23381FJ-80
s PIN DESCRIPTION
Pin Name
A19 to A0
A21, A20
DQ15 to DQ0
CEf
CE1r
CE2r
OE
WE
RY/BY
UB
LB
RESET
WP/ACC
N.C.
VSS
VCCf
VCCr
Function
Address Inputs (Common)
Address Inputs (Flash)
Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (FCRAM)
Chip Enable (FCRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (FCRAM)
Lower Byte Control (FCRAM)
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect/Acceleration (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (FCRAM)
s BLOCK DIAGRAM
A21 to A0
WP/ACC
RESET
CEf
A21 to A0
VCCf
VSS
64 M bit
Flash Memory
RY/BY
DQ15 to DQ0
LB
UB
WE
OE
CE1r
CE2r
VCCr
VSS
A19 to A0
16 M bit
FCRAM
DQ15 to DQ0
Input/Output
I
I
I/O
I
I
I
I
I
O
I
I
I
I

Power
Power
Power
DQ15 to DQ0
5