MB84VD23381FJ Datasheet, PDF (47/54 Pages) Fujitsu Component Limited. – Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

MB84VD23381FJ-80
• POWER DOWN Timing (FCRAM)
CE1r
CE2r
DQ
tCSP
Power Down Entry
tCHS
tC2LP
High-Z
Power Down Mode
tCHH
Power Down Exit
• POWER-UP Timing 1 (FCRAM)
CE1r
CE2r
*
tC2LH
tCHS
tCHH
VCCr
0V
VCCr Min
* : It is recommended CE2r to kept at Low during VCCr power-up.
The tC2LH specifies after VCCr reaches specified minimum level.
• POWER-UP Timing 2 (FCRAM)
CE1r
CE2r
tC2HL
tC2HL
tCSP
tC2LP
tCHS
tCHH
VCCr
0V
VCCr Min
* : The tC2LH specifies from CE2r Low to High transition after VCCr reaches specified minimum level.
CE1r must be brought to High prior to or together with CE2r Low to High transition.
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