MB84VD23381FJ Datasheet, PDF (27/54 Pages) Fujitsu Component Limited. – Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

MB84VD23381FJ-80
• Write Cycle (CEf control) (Flash)
Address
3rd Bus Cycle
555h
PA
tWC
tAS tAH
WE
OE
CEf
Data
tWS
tWH
tGHEL
tCP tCPH
tDS
A0h
tDH
PD
Data Polling
PA
tWHWH1
DQ7 DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
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