MB84VD23381FJ Datasheet, PDF (31/54 Pages) Fujitsu Component Limited. – Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM

MB84VD23381FJ-80
• Bank-to-bank Read/Write Timing Diagram (Flash)
Address
CEf
Read
tRC
BA1
Command
tWC
BA2
(555h)
tAS
tAH
Read
tRC
BA1
tACC
tCE
Command
tWC
BA2
(PA)
tOE
OE
WE
tGHWL
tOEH
tWP
tDS ^tDH
tDF
tDF
Read
tRC
Read
tRC
BA1
BA2
(PA)
tAS
tAHT
tCEPH
DQ
Valid Valid
Output Intput
Valid Valid
Output Intput
Valid
Output
Status
(A0h)
(PD)
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address corresponding to Bank 1
BA2 : Address corresponding to Bank 2
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